Abstract: A current integration-based in-memory spiking neural network (SNN) uses charge-domain computation which is naturally compatible with working mechanisms of neurons. In one aspect, silicon-based SRAM cells are included in memory cells of a synaptic array, which can avoid non-idealities caused by resistive NVM materials. Additionally, a modified NVM cell is provided, which benefits from the in-memory SNN architecture design. When SRAM cells are used as memory cells in the synaptic array, post-neuron circuits are designed accordingly so that the in-memory SNN architecture can be used in computation with multi-bit synaptic weights by combining a programmable number of columns. Further, for computation with multi-bit synaptic weights, a circuit is designed to be time-multiplexed for resource sharing to achieve improved area and energy efficiency.

Abstract: A mixed-signal in-memory computing sub-cell only requires 9 transistors for 1-bit multiplication. A computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. A MAC array for performing MAC operations, includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. A differential version of the MAC array provides improved computation error tolerance and an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, allowing the computing module to have a reduced area and suffer from fewer computational errors.

Abstract: In one aspect, a time division interleaving band-pass filter can be used in voice activity detection, which operates at different central frequencies in respective intervals of a predetermined period of time. The band-pass filter circuitry includes multiple band-pass filtering channels sharing a common transistor circuit, bias circuit and current mirror circuit. The multiple band-pass filtering channels operate in a time division interleaving manner, which enables the sharing of the common set of band-pass filter circuitry components. Thus, the present invention allows a reduced chip area as the area does not increase proportionally with the number of filtering channels. The invention also mitigates the influence of transistor fabrication variations on the filter's central frequencies.

Abstract: A mixed-signal in-memory computing sub-cell only requires 9 transistors for 1-bit multiplication. A computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is a differential version of the MAC array with improved computation error tolerance and an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, thus allowing the computing module to have a reduced area and suffer from less computation errors. Also proposed is a method of fully taking advantage of data sparsity to lower the ADC block's power consumption.

Abstract: In one aspect, a time division interleaving band-pass filter can be used in voice activity detection, which operates at different central frequencies in respective intervals of a predetermined period of time. The band-pass filter circuitry includes multiple band-pass filtering channels sharing a common transistor circuit, bias circuit and current mirror circuit. The multiple band-pass filtering channels operate in a time division interleaving manner, which enables the sharing of the common set of band-pass filter circuitry components. Thus, the present invention allows a reduced chip area as the area does not increase proportionally with the number of filtering channels. The invention also mitigates the influence of transistor fabrication variations on the filter's central frequencies.

Abstract: A mixed-signal in-memory computing sub-cell requires only 9 transistors for 1-bit multiplication. In one aspect, there is a computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and common transistors. As a result, the average number of transistors in each sub-cell is close to 6. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is a differential version of the MAC array with improved computation error tolerance. Also proposed is an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, thus allowing the computing module to have a reduced area and suffer from less computation errors.

Abstract: A band-pass filter is described comprising a first first-order filter stage comprising a first resistor characterized by a first impedance and connected to a first node, referred to as a filter input node, and, through a second node to a first reactive component connected to a third node, the first impedance being such that a first current therethrough is dependent on the difference between the voltages at the first and second nodes; and a second first-order filter stage comprising a second resistor characterized by a second impedance and connected to the second node, and, through a fourth node, to a second reactive component connected to a fifth node. The second impedance is such that a second current therethrough is dependent on the negative of the sum of the voltages at the second and fourth nodes. The band-pass filter further comprises summing means for summing the voltages at the second and fourth nodes to output a voltage at a sixth node.

Abstract: A band-pass filter is described comprising a first first-order filter stage comprising a first resistor characterised by a first impedance and connected to a first node, referred to as a filter input node, and, through a second node to a first reactive component connected to a third node, the first impedance being such that a first current therethrough is dependent on the difference between the voltages at the first and second nodes; and a second first-order filter stage comprising a second resistor characterised by a second impedance and connected to the second node, and, through a fourth node, to a second reactive component connected to a fifth node. The second impedance is such that a second current therethrough is dependent on the negative of the sum of the voltages at the second and fourth nodes. The band-pass filter further comprises summing means for summing the voltages at the second and fourth nodes to output a voltage at a sixth node.