Patents by Inventor Minkle Eldho Paul
Minkle Eldho Paul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11349492Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.Type: GrantFiled: December 4, 2020Date of Patent: May 31, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sovan Ghosh, Minkle Eldho Paul, Laxmi Vivek Tripurari, Amal Kumar Kundu
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Patent number: 11258452Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.Type: GrantFiled: September 30, 2020Date of Patent: February 22, 2022Assignee: Texas Instruments IncorporatedInventors: Yujendra Mitikiri, Minkle Eldho Paul, Anukruti Chakraborty
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Patent number: 11206035Abstract: An analog to digital (A/D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S/H) output. The A/D converter also includes a voltage comparator having a first input coupled to the S/H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage. The A/D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.Type: GrantFiled: December 3, 2019Date of Patent: December 21, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rahul Vijay Kulkarni, Shridhar More, Amal Kumar Kundu, Minkle Eldho Paul
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Publication number: 20210119638Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.Type: ApplicationFiled: December 4, 2020Publication date: April 22, 2021Inventors: Sovan GHOSH, Minkle Eldho PAUL, Laxmi Vivek TRIPURARI, Amal KUMAR KUNDU
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Publication number: 20210013895Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Yujendra MITIKIRI, Minkle Eldho PAUL, Anukruti CHAKRABORTY
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Patent number: 10886933Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.Type: GrantFiled: October 18, 2019Date of Patent: January 5, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sovan Ghosh, Minkle Eldho Paul, Laxmi Vivek Tripurari, Amal Kumar Kundu
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Patent number: 10868558Abstract: An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator coupled to the CDAC, and a successive approximation register (SAR) control circuit coupled to the CDAC and the comparator. The SAR control circuit is configured to successively select bits of a digital output value. The SAR control circuit is also configured to, after selection of the bits of the digital output value: maintain a state of first switches of the CDAC applied to select a most significant bit of the digital output value, and revert second switches of the CDAC applied to select bits of the digital output value having significance lower than the most significant bit to a state of the second switches prior to selection of the most significant bit.Type: GrantFiled: December 13, 2019Date of Patent: December 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Laxmi Vivek Tripurari, Sovan Ghosh, Minkle Eldho Paul
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Patent number: 10833690Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.Type: GrantFiled: October 16, 2019Date of Patent: November 10, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yujendra Mitikiri, Minkle Eldho Paul, Anukruti Chakraborty
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Publication number: 20200295773Abstract: An analog to digital (A/D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S/H) output. The A/D converter also includes a voltage comparator having a first input coupled to the S/H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage. The A/D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.Type: ApplicationFiled: December 3, 2019Publication date: September 17, 2020Inventors: Rahul Vijay Kulkarni, Shridhar More, Amal Kumar Kundu, Minkle Eldho Paul
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Publication number: 20200067518Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.Type: ApplicationFiled: October 16, 2019Publication date: February 27, 2020Inventors: Yujendra MITIKIRI, Minkle Eldho PAUL, Anukruti CHAKRABORTY
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Patent number: 10483994Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.Type: GrantFiled: February 22, 2018Date of Patent: November 19, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yujendra Mitikiri, Minkle Eldho Paul, Anukruti Chakraborty
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Publication number: 20190207615Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.Type: ApplicationFiled: February 22, 2018Publication date: July 4, 2019Inventors: Yujendra MITIKIRI, Minkle Eldho PAUL, Anukruti CHAKRABORTY
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Patent number: 8766839Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.Type: GrantFiled: September 7, 2012Date of Patent: July 1, 2014Assignee: Texas Instruments IncorporatedInventors: Seetharaman Janakiraman, Minkle Eldho Paul
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Publication number: 20140070968Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.Type: ApplicationFiled: September 7, 2012Publication date: March 13, 2014Applicant: Texas Instruments IncorporatedInventors: Seetharaman Janakiraman, Minkle Eldho Paul