Patents by Inventor Minoru Ariyama

Minoru Ariyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110133812
    Abstract: Provided is a physical quantity sensor capable of improving physical quantity detection precision thereof. The physical quantity sensor includes a bridge resistance type physical quantity detection element for generating a voltage based on a bias current and a physical quantity, a current supply circuit for supplying the bias current to the physical quantity detection element, and a leakage current control circuit for causing leakage currents flowing when switches of the current supply circuit are in an off state to flow into a ground terminal.
    Type: Application
    Filed: December 6, 2010
    Publication date: June 9, 2011
    Inventors: Manabu Fujimura, Minoru Ariyama, Daisuke Muraoka, Tomoki Hikichi
  • Patent number: 7956598
    Abstract: To provide a variable voltage dividing circuit capable of changing voltage values of a detection point and a release point along with a change in power supply voltage without changing a hysteresis width.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: June 7, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Minoru Ariyama
  • Publication number: 20110127989
    Abstract: Provided is a constant current circuit capable of low current consumption operation, which is prevented from repeating a start-up state and a zero steady state and entering an oscillating state when power is activated. When power is activated, until a node (A) reaches a start-up state, an excitation current is continued to be supplied to a node (B), to thereby reliably start up the constant current circuit in a short period of time without repeating the start-up state and the zero steady state.
    Type: Application
    Filed: November 30, 2010
    Publication date: June 2, 2011
    Inventors: Tomoki Hikichi, Minoru Ariyama, Daisuke Muraoka, Manabu Fujimura
  • Publication number: 20110074404
    Abstract: Provided is a magnetic sensor circuit of low power consumption, in which a magnetic detection level less depends on a resistance value of an internal resistor of a power source. A comparator circuit compares a voltage which is based on a magnetic field and generated after sampling under a state in which power is supplied to mainly a Hall element and an amplifier circuit to drop a power supply voltage, with a reference voltage after sampling under the same state. Both the voltages are generated based on the power supply voltage dropped by an internal resistor. Therefore, the magnetic detection level less depends on a resistance value of the internal resistor. The comparator circuit may be disabled during a sample period, and the Hall element and the amplifier circuit may be disabled during a comparison period, and hence power consumption of the magnetic sensor circuit is reduced by corresponding power.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 31, 2011
    Inventors: Tomoki Hikichi, Minoru Ariyama
  • Patent number: 7915964
    Abstract: A variable frequency oscillating circuit has an oscillating circuit that undergoes an oscillation operation. The oscillating circuit has at least one inverter and at least one capacitor forming a circuit in a ring oscillator configuration. A current circuit outputs a current based on a frequency control signal controlling a frequency of a clock signal output from the oscillating circuit. A pulse generating circuit generates a pulse when the frequency control signal is switched from low to high and from high to low. The oscillating circuit stops an oscillation operation by stopping a charge/discharge operation of the at least one capacitor when the pulse is generated by the pulse generating circuit.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: March 29, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Minoru Ariyama
  • Publication number: 20100308815
    Abstract: Provided is a magnetic sensor device including: a switching circuit that controls switching of a terminal pair of the magnetoelectric conversion element to which a supply voltage is applied and a terminal pair to which detection voltage of a magnetic intensity is output; a differential amplifier that differentially amplifies the detection voltage; a first capacitor connected to a first output terminal of the differential amplifier; a second switch connected to a second output terminal of the differential amplifier; a comparator that has a first input terminal connected to the first capacitor and a second input terminal connected to the second switch; a first switch connected between the first input terminal and an output terminal of the comparator; and a second capacitor connected to the second input terminal of the comparator; and a detection voltage setting circuit connected to the second capacitor, in which effects of respective offset voltages of the magnetoelectric conversion element, the amplifier, and
    Type: Application
    Filed: May 13, 2010
    Publication date: December 9, 2010
    Inventors: Daisuke Muraoka, Minoru Ariyama, Tomoki Hikichi, Manabu Fujimura
  • Patent number: 7721169
    Abstract: A scanning circuit has path switches connected between a plurality of data flip-flop circuits of the scanning circuit for sequentially reading an output signal in synchronism with a clock. A plurality of control signal lines select the path switches to arbitrarily skip reading of the flip-flop circuits that do not require the scanning circuit and always fix a potential of the skipped data flip-flop circuit. Only the arbitrary data is read, and in the case where unnecessary data exists, reading is skipped, to thereby increase the read rate.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: May 18, 2010
    Assignee: Seiko Instruments Inco.
    Inventors: Masahiro Yokomichi, Satoshi Machida, Yoshihiro Shibuya, Yukito Kawahara, Minoru Ariyama
  • Publication number: 20100117715
    Abstract: Provided is a sensor circuit that is small in circuit scale, but is capable of temperature compensation. A reference voltage circuit (BL1) which compensates a temperature includes only a voltage divider circuit, and hence the sensor circuit is small in circuit scale. The sensor circuit is also capable of temperature compensation because temperature changes of reference voltages (VTH11 and VTH12) and reference voltages (VTH21 and VTH22) match a temperature change of an output signal (OUTA) of an amplifier circuit (AMP1) which is caused by a temperature change of an output signal of a Hall element (HAL1).
    Type: Application
    Filed: November 9, 2009
    Publication date: May 13, 2010
    Inventor: Minoru Ariyama
  • Publication number: 20100117637
    Abstract: Provided is a sensor circuit that is small in circuit scale, but is capable of temperature compensation. A reference voltage circuit (BL1) which compensates a temperature includes only a voltage divider circuit, and hence the sensor circuit is small in circuit scale. The sensor circuit is also capable of temperature compensation because temperature changes of a reference voltage (VTH1) and a reference voltage (VTH2) match a temperature change of an output signal (OUTA) of an amplifier circuit (AMP1) which is caused by a temperature change of an output signal of a Hall element (HAL1).
    Type: Application
    Filed: November 9, 2009
    Publication date: May 13, 2010
    Inventor: Minoru Ariyama
  • Publication number: 20090079411
    Abstract: To provide a variable voltage dividing circuit capable of changing voltage values of a detection point and a release point along with a change in power supply voltage without changing a hysteresis width.
    Type: Application
    Filed: August 15, 2008
    Publication date: March 26, 2009
    Applicant: Seiko Instruments Inc.
    Inventor: Minoru ARIYAMA
  • Patent number: 7508258
    Abstract: Provided is a chopper amplifier circuit capable of eliminating an influence of a slew rate of an amplifier and suppressing spike generation to thereby obtain an output signal having little harmonic distortion. The chopper amplifier circuit according to the present invention includes: a first chopper circuit for chopping an input signal by a first pulse and a second pulse shifted from each other in phase by a half cycle, switching a relation of connection between an input terminal pair and an output terminal pair at a timing of the chopping, and outputting the input signal as a modulated signal; an amplifier for amplifying the modulated signal and outputting the modulated signal thus amplified as an amplified signal; a first sample hold circuit for holding the amplified signal at the first pulse and outputting the amplified signal at the second pulse; and a second sample hold circuit for holding the amplified signal at the second pulse and outputting the amplified signal at the first pulse.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: March 24, 2009
    Assignees: Seiko Instruments Inc., Gakkouhoujin Chikoujigakuen
    Inventors: Hirokazu Yoshizawa, Ryoichi Anzai, Toshiyuki Uchida, Akira Takeda, Minoru Ariyama, Atsushi Igarashi
  • Publication number: 20090058542
    Abstract: Provided is a variable frequency oscillating circuit which has a small circuit size and is unlikely to cause a semiconductor device to malfunction. One oscillating circuit (3) is used, and thus the circuit size is not increased. When a frequency control signal (SF) is switched, constant currents (I2 and I3) are each switched, and ringing is generated in the constant currents (I2 and I3), a pulse signal (SP) becomes high to be input to the oscillating circuit (3) during the ringing, and a clock signal (CLK) output from the oscillating circuit (3) in response to the pulse signal (SP) is fixed to low, with the result that the oscillating circuit (3) stops a regular oscillation. As a result, a clock signal having an unintended frequency is not generated.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 5, 2009
    Inventor: Minoru Ariyama
  • Patent number: 7479826
    Abstract: Provided is a chopper amplifier circuit capable of reducing an offset voltage of a sensor bridge and temperature characteristics of the offset voltage. An offset adjusting voltage generation circuit for generating a voltage equal to an offset voltage of a sensor bridge and an offset temperature characteristics adjusting voltage generation circuit for generating a voltage having temperature characteristics equal to those of the offset voltage are provided. These output voltages are chopper-modulated and subtracted from a chopper-modulated output signal of the sensor bridge.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: January 20, 2009
    Assignees: Seiko Instruments Inc., Gakkouhoujin Chikoujigakuen
    Inventors: Hirokazu Yoshizawa, Ryoichi Anzai, Toshiyuki Uchida, Minoru Ariyama, Atsushi Igarashi, Akira Takeda
  • Publication number: 20070222509
    Abstract: Provided is a chopper amplifier circuit capable of eliminating an influence of a slew rate of an amplifier and suppressing spike generation to thereby obtain an output signal having little harmonic distortion. The chopper amplifier circuit according to the present invention includes: a first chopper circuit for chopping an input signal by a first pulse and a second pulse shifted from each other in phase by a half cycle, switching a relation of connection between an input terminal pair and an output terminal pair at a timing of the chopping, and outputting the input signal as a modulated signal; an amplifier for amplifying the modulated signal and outputting the modulated signal thus amplified as an amplified signal; a first sample hold circuit for holding the amplified signal at the first pulse and outputting the amplified signal at the second pulse; and a second sample hold circuit for holding the amplified signal at the second pulse and outputting the amplified signal at the first pulse.
    Type: Application
    Filed: February 6, 2007
    Publication date: September 27, 2007
    Inventors: Hirokazu Yoshizawa, Ryoichi Anzai, Toshiyuki Uchida, Akira Takeda, Minoru Ariyama, Atsushi Igarashi
  • Publication number: 20070146065
    Abstract: Provided is a chopper amplifier circuit capable of reducing an offset voltage of a sensor bridge and temperature characteristics of the offset voltage. An offset adjusting voltage generation circuit for generating a voltage equal to an offset voltage of a sensor bridge and an offset temperature characteristics adjusting voltage generation circuit for generating a voltage having temperature characteristics equal to those of the offset voltage are provided. These output voltages are chopper-modulated and subtracted from a chopper-modulated output signal of the sensor bridge.
    Type: Application
    Filed: August 4, 2006
    Publication date: June 28, 2007
    Inventors: Hirokazu Yoshizawa, Ryoichi Anzai, Toshiyuki Uchida, Minoru Ariyama, Atsushi Igarashi, Akira Takeda
  • Patent number: 6725436
    Abstract: To provide a resistor circuit with which a resistance ratio among voltage division resistors in a semiconductor integrated circuit can be realized with high accuracy. The resistor circuit of the present invention includes: a reference resistor portion; and a resistor portion including resistor elements and fuse connected in parallel with the resistor elements, respectively, for trimming the resistor elements. The resistor elements are arranged in order from the resistor element having a largest resistance value so as to be adjacent to the reference resistor portion in the periphery of the reference resistor portion. As a result, it is possible to obtain accurately the ratio between a resistance value of a reference resistor and a desired resistance value determined with the ratio from the resistance value of the reference resistor.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: April 20, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Toshiyuki Koike, Yoshihide Kanakubo, Minoru Ariyama
  • Publication number: 20030156105
    Abstract: A scanning circuit has path switches connected between a plurality of data flip-flop circuits of the scanning circuit for sequentially reading an output signal in synchronism with a clock. A plurality of control signal lines select the path switches to arbitrarily skip reading of the flip-flop circuits that do not require the scanning circuit and always fix a potential of the skipped data flip-flop circuit. Only the arbitrary data is read, and in the case where unnecessary data exists, reading is skipped, to thereby increase the read rate.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 21, 2003
    Inventors: Masahiro Yokomichi, Satoshi Machida, Yoshihiro Shibuya, Yukito Kawahara, Minoru Ariyama
  • Publication number: 20030154456
    Abstract: To provide a resistor circuit with which a resistance ratio among voltage division resistors in a semiconductor integrated circuit can be realized with high accuracy. The resistor circuit of the present invention includes: a reference resistor portion; and a resistor portion including resistor elements and fuse connected in parallel with the resistor elements, respectively, for trimming the resistor elements. The resistor elements are put to be arranged in order from the resistor element having a largest resistance value so as to be adjacent to the reference resistor portion in the periphery of the reference resistor portion. As a result, it is possible to obtain accurately the ratio between a resistance value of a reference resistor and a desired resistance value determined with the ratio from the resistance value of the reference resistor.
    Type: Application
    Filed: October 9, 2002
    Publication date: August 14, 2003
    Inventors: Toshiyuki Koike, Yoshihide Kanakubo, Minoru Ariyama