Abstract: In a fluorescent display tube having an electrostatic capacitor type touch switch portion on a front plate, a shield electrode is provided between a filament cathode and the touch switch portion. Electrons emitted from the filament cathode are prevented from irradiating on the touch switch portion and the touch switch portion and a neighbor thereof are prevented from being charged up, thereby an operation of the electrostatic capacitor type touch switch becomes stable.

Abstract: A multiplex anode matrix fluorescent display capable of allowing a duty cycle thereof to be multiple times that of the prior art multiplex anode matrix fluorescent display is provided without changing the structure of the prior art multiplex anode matrix fluorescent display.

Abstract: A controller driver for a fluorescent display unit for use in a display system is connected to a host micom which controls operations of the display system and to a display unit. The controller driver comprises an interface, a decoder, a display RAM, an electrode driver, a controller and a clock generator. The interface transfers data from/to the host micom. The decoder identifies and divides the data received from the interface into command data and display data. The display data includes anode data and grid data and the electrode driver includes therein an anode driver and a grid driver. The display RAM stores the display data received from the decoder. The electrode driver actuates the display unit by using the command data and the display data. The controller sets a driving mode and a display mode by using the command data, retrieves the display data and provides the display data to the electrode driver.

Abstract: A multiplex anode driver circuit is provided that enables a reduced RAM capacity, an improved speed, and slimmed hardware. The multiplex anode driver circuit outputs anode data in sync with the timing when two adjacent grids are sequentially scanned in the direction of a row of anodes. The anode driver circuit has the shift register allocated with an even-numbered grid timing and the shift register allocated with an odd-numbered grid timing, in a two system. In the shift register, the registers are connected to the latch circuits, which hold anode data of the registers. In the shift register, the registers are connected to the latch circuits which hold anode data of the registers. The blanking input to the latch circuit associated with the shift register and the blanking input to the latch circuit associated with the shift register are released alternatively while the even-numbered grid timing and the odd-numbered grid timing are selected. Thus, anode data is transferred to the memory.

Abstract: A multiplex anode matrix fluorescent display capable of allowing a duty cycle thereof to be multiple times that of the prior art multiplex anode matrix fluorescent display is provided without changing the structure of the prior art multiplex anode matrix fluorescent display. Anode electrodes 3 are arranged in the form of a matrix. A plurality of grid electrodes 2 is prepared in such a way that a column of the grid electrodes corresponds to two columns of the anode electrodes 3 and each of the anode electrodes 3 and the grid electrodes 2 are divided into two areas to form anode wiring patterns in the form of quadruple anode matrix at each of the area. Anode terminals P1A˜P(4×m)A connecting each of the arrangement numbers 1 to 4 in each row of the anode A part to a common terminal are drawn from left end. On the other hand, anode terminals P1B˜P(4×m)B connecting each of the arrangement numbers 1 to 4 in each row of the anode B part to a common terminal are drawn from right end.

Abstract: A multiplex anode driver circuit is provided that enables a reduced RAM capacity, an improved speed, and slimmed hardware. The multiplex anode driver circuit outputs anode data in sync with the timing when two adjacent grids are sequentially scanned in the direction of a row of anodes. The anode driver circuit has the shift register allocated with an even-numbered grid timing and the shift register allocated with an odd-numbered grid timing, in a two system. In the shift register, the registers are connected to the latch circuits, which hold anode data of the registers. In the shift register, the registers are connected to the latch circuits which hold anode data of the registers. The blanking input to the latch circuit associated with the shift register and the blanking input to the latch circuit associated with the shift register are released alternatively while the even-numbered grid timing and the odd-numbered grid timing are selected. Thus, anode data is transferred to the memory.