Patents by Inventor Minoru Ishida

Minoru Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210084249
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 18, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Yoshiaki KITANO, Hirofumi YAMASHITA, Minoru ISHIDA
  • Patent number: 10923517
    Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: February 16, 2021
    Assignee: Sony Corporation
    Inventors: Harumi Tanaka, Yoshiaki Masuda, Shinji Miyazawa, Minoru Ishida
  • Patent number: 10903503
    Abstract: The present invention is a catalyst for a solid polymer fuel cell including: catalyst particles of platinum, cobalt and manganese; and a carbon powder carrier supporting the catalyst particles, wherein the component ratio (molar ratio) of the platinum, cobalt and manganese of the catalyst particles is of Pt:Co:Mn=1:0.06 to 0.39:0.04 to 0.33, and wherein in an X-ray diffraction analysis of the catalyst particles, the peak intensity ratio of a Co—Mn alloy appearing around 2?=27° is 0.15 or less on the basis of a main peak appearing around 2?=40°. It is particularly preferred that the catalyst have a peak ratio of a peak of a CoPt3 alloy and an MnPt3 alloy appearing around 2?=32° of 0.14 or more on the basis of a main peak.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 26, 2021
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventors: Minoru Ishida, Koichi Matsutani
  • Patent number: 10892496
    Abstract: The present invention provides a catalyst for a solid polymer fuel cell, having excellent initial activity and good durability and a production method thereof. The present invention is a catalyst for a solid polymer fuel cell, including catalyst particles composed of platinum or a platinum alloy supported on a carbon powder carrier, the catalyst having sulfo groups (—SO3H) at least on the catalyst particles, and the catalyst further having a fluorine compound having a C—F bond supported at least on the catalyst particles. It is preferred in the catalyst of the present invention that sulfur content is 800 ppm or more and 5000 ppm or less based on the mass of the whole catalyst and the amount of the fluorine compound is 3 mass % or more and 24 mass % or less based on the mass of the whole catalyst.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: January 12, 2021
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventors: Minoru Ishida, Koichi Matsutani
  • Patent number: 10886869
    Abstract: A control apparatus is applied to a vehicle including (i) a rotating electrical machine and (ii) a wheel speed sensor detecting a wheel speed. The control apparatus sets a rotation angle of the rotating electrical machine based on an estimated value of the rotation angle which is estimated based on a detection value of the wheel speed sensor.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: January 5, 2021
    Assignee: DENSO CORPORATION
    Inventors: Minoru Ishida, Naoki Katayama, Tsubasa Sakuishi, Yuki Takahashi
  • Patent number: 10875418
    Abstract: In a charging control apparatus, a supply power requestor requests an external power source to output supply power having a constant voltage and a constant current. A voltage conversion instructor instructs a voltage conversion device to perform voltage conversion of the supply power from the external power source such that converted supply power has a charging voltage and a charging current that are respectively within allowable charging-voltage range and allowable charging-current range. The voltage conversion instructor instructs the voltage conversion device to output the converted supply power to the power storage to thereby charge the power storage.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 29, 2020
    Assignee: DENSO CORPORATION
    Inventors: Minoru Ishida, Naoki Katayama, Tsubasa Sakuishi
  • Publication number: 20200365639
    Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Applicant: Sony Corporation
    Inventors: Hiroyasu MATSUGAI, Hiroyuki ITOU, Suguru SAITO, Keiji OHSHIMA, Masanori IWASAKI, Toshihiko HAYASHI, Shuzo SATO, Nobutoshi FUJII, Hiroshi TAZAWA, Toshiaki SHIRAIWA, Minoru ISHIDA
  • Publication number: 20200357838
    Abstract: Provided is a laminated lens structure capable of corresponding various optical parameters. The laminated lens structure includes at least one or more sheets of first lens-attached substrates and at least one or more sheets of second lens-attached substrates as a lens-attached substrate including a lens resin portion that forms a lens, and a carrier substrate that carries the lens resin portion. The carrier substrate of the first lens-attached substrates is constituted by laminating a plurality of sheets of carrier configuration substrates in a thickness direction, and the carrier substrate of the second lens-attached substrates is constituted by one sheet of carrier configuration substrate. For example, the present technology is applicable to a camera module and the like.
    Type: Application
    Filed: August 17, 2018
    Publication date: November 12, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Munekatsu FUKUYAMA, Hirotaka YOSHIOKA, Kunihiko HIKICHI, Atsushi YAMAMOTO, Kaori TAKIMOTO, Minoru ISHIDA
  • Patent number: 10818717
    Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: October 27, 2020
    Assignee: Sony Corporation
    Inventors: Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Masanori Iwasaki, Toshihiko Hayashi, Shuzo Sato, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Publication number: 20200251511
    Abstract: The present disclosure relates to a solid-state imaging apparatus that can further downsize the size of the apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, at which a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned is formed, and a second structure body, at which an output circuit unit for outputting a pixel signal outputted from the pixels to the outside of the apparatus is formed. The output circuit unit, a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the pixel array unit of the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Applicant: SONY CORPORATION
    Inventors: Harumi TANAKA, Yoshiaki MASUDA, Shinji MIYAZAWA, Minoru ISHIDA
  • Publication number: 20200251519
    Abstract: The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Applicant: SONY CORPORATION
    Inventors: Yoshiaki MASUDA, Minoru ISHIDA
  • Publication number: 20200243591
    Abstract: [Object] To further improve performance of a solid-state imaging device. [Solution] There is provided a solid-state imaging device including: a first substrate; a second substrate; and a third substrate that are stacked in this order. The first substrate includes a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate. The first semiconductor substrate has a pixel unit formed thereon. The pixel unit has pixels arranged thereon. The second substrate includes a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate. The second semiconductor substrate has a circuit formed thereon. The circuit has a predetermined function. The third substrate includes a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate. The third semiconductor substrate has a circuit formed thereon. The circuit has a predetermined function.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 30, 2020
    Inventors: TADASHI IIJIMA, TAKATOSHI KAMESHIMA, IKUE MITSUHASHI, HIROSHI HORIKOSHI, HIDETO HASHIGUCHI, REIJIROH SHOHJI, MINORU ISHIDA, MASAKI HANEDA
  • Patent number: 10712543
    Abstract: A positional shift of a lens of a stacked lens structure is reduced. A plurality of through-holes is formed at a position shifted from a first target position on a substrate according to a first shift. A lens is formed on an inner side of each of the through-holes using a first mold in which a plurality of first transfer surfaces is disposed at a position shifted from a predetermined second target position according to a second shift and a second mold in which a plurality of second transfer surfaces is disposed at a position shifted from a predetermined third target position according to a third shift. The plurality of substrates having the lenses formed therein is formed according to direct bonding, and the plurality of stacked substrates is divided. The present technique can be applied to a stacked lens structure or the like, for example.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 14, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kunihiko Hikichi, Koichi Takeuchi, Toshihiro Kurobe, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Patent number: 10690814
    Abstract: Influence of chipping in case of dicing a plurality of stacked substrates is reduced. Provided is a semiconductor device where a substrate, in which a groove surrounding a pattern configured with a predetermined circuit or part is formed, is stacked. The present technology can be applied to, for example, a stacked lens structure where through-holes are formed in each substrate and lenses are disposed in inner sides of the through-holes, a camera module where a stacked lens structure and a light-receiving device are incorporated, a solid-state imaging device where a pixel substrate and a control substrate are stacked, and the like.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: June 23, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Toshiaki Shiraiwa, Masaki Okamoto, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Minoru Ishida
  • Patent number: 10680026
    Abstract: The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: June 9, 2020
    Assignee: SONY CORPORATION
    Inventors: Yoshiaki Masuda, Minoru Ishida
  • Publication number: 20200176786
    Abstract: The present invention relates to a catalyst for a solid polymer fuel cell that includes catalyst particles supported on a carbon powder carrier, the catalyst particles containing platinum, cobalt, and manganese. In the catalyst particles of the catalyst, the component ratio of platinum, cobalt, and manganese is Pt:Co:Mn=1:0.25 to 0.28:0.07 to 0.10 in a molar ratio, the average particle size is 3.4 to 5.0 nm, and further, in the particle size distribution of the catalyst particles, the proportion of catalyst particles having a particle size of 3.0 nm or less in the entire catalyst particles is 37% or less on a particle number basis. Then, a fluorine compound having a C—F bond is supported at least on the surface of the catalyst particles. The present invention is, with respect to the above ternary alloy catalyst, an invention particularly effective in improving the durability.
    Type: Application
    Filed: September 20, 2018
    Publication date: June 4, 2020
    Applicant: TANAKA KIKINZOKU KOGYO K.K.
    Inventor: Minoru ISHIDA
  • Patent number: 10672809
    Abstract: The present disclosure relates to a solid-state imaging apparatus that is configured by laminating a first structure body, at which a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned is formed, and a second structure body, at which an output circuit unit for outputting a pixel signal outputted from the pixels to the outside of the apparatus is formed. The output circuit unit, a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the pixel array unit of the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: June 2, 2020
    Assignee: Sony Corporation
    Inventors: Harumi Tanaka, Yoshiaki Masuda, Shinji Miyazawa, Minoru Ishida
  • Patent number: 10627549
    Abstract: Substrates with lenses having lenses disposed therein are aligned with high accuracy. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are direct-bonded and stacked based on an alignment mark. The alignment mark is formed simultaneously with the through-hole. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 21, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Atsushi Yamamoto, Koichi Takeuchi, Toshihiro Kurobe, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Publication number: 20200105814
    Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 2, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hideto HASHIGUCHI, Reijiroh SHOHJI, Hiroshi HORIKOSHI, Ikue MITSUHASHI, Tadashi IIJIMA, Takatoshi KAMESHIMA, Minoru ISHIDA, Masaki HANEDA
  • Publication number: 20200105813
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 2, 2020
    Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA