Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1-yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.

Abstract: A lateral heterojunction bipolar transistor comprises a first semiconductor layer in a mesa configuration disposed on an insulating layer, a second semiconductor layer formed by epitaxial growth on the side surfaces of the first semiconductor layer and having a band gap different from that of the first semiconductor layer, and a third semiconductor layer formed by epitaxial growth on the side surfaces of the second semiconductor layer and having a band gap different from that of the second semiconductor layer. The first semiconductor layer serves as a collector of a first conductivity type. At least a part of the second semiconductor layer serves as an internal base layer of a second conductivity type. At least a part of the third semiconductor layer serves as an emitter operating region of the first conductivity type. The diffusion of an impurity is suppressed in the internal base formed by epitaxial growth.

Abstract: A B-doped Si1−x−yGexCy layer 102 (where 0<x<1, 0.01≦y<1) is epitaxially grown on a Si substrate 101 using a UHV-CVD process. In the meantime, in-situ doping is performed using B2H6 as a source gas of boron (B) which is an impurity (dopant). Next, the Si1−x−yGexCy layer 102 is annealed to form a B-doped Si1−x−yGexCy crystalline layer 103. In this case, the annealing temperature is set preferably at between 700° C. and 1200° C., both inclusive, and more preferably at between 900° C. and 1000° C., both inclusive.

Abstract: A lateral heterojunction bipolar transistor comprises a first semiconductor layer in a mesa configuration disposed on an insulating layer, a second semiconductor layer formed by epitaxial growth on the side surfaces of the first semiconductor layer and having a band gap different from that of the first semiconductor layer, and a third semiconductor layer formed by epitaxial growth on the side surfaces of the second semiconductor layer and having a band gap different from that of the second semiconductor layer. The first semiconductor layer serves as a collector of a first conductivity type. At least a part of the second semiconductor layer serves as an internal base layer of a second conductivity type. At least a part of the third semiconductor layer serves as an emitter operating region of the first conductivity type. The diffusion of an impurity is suppressed in the internal base formed by epitaxial growth.

Abstract: Source gases and atomic hydrogen are alternately supplied onto a substrate on which a crystal is to be grown. By exposing a surface of the substrate to the atomic hydrogen, the ratio of Ge atoms attached to H atoms to all Ge atoms present on the outermost surface where growth is proceeding is increased compared with that prior to the exposure to the atomic hydrogen. If H atoms are attached to Ge atoms on the outermost surface, the phenomenon occurs in which the Ge atoms are interchanged with Si atoms present in the underlying layer. As a result, a higher proportion of Ge atoms are interchanged with Si atoms than in a conventional manufacturing method which does not involve the exposure to the atomic hydrogen. This reduces the ratio of Ge atoms to all atoms on the outermost surface where growth is proceeding and renders C atoms having low affinity with Ge atoms more likely to occupy lattice positions in the crystal.

Abstract: In a channel layer made of SiGe containing C, the Ge composition varies linearly from 0% to 50% from one end closer to a silicon buffer layer toward the other end closer to a silicon cap layer, and C is contained at 0.5% selectively in a region where the Ge composition is 40% to 50% (i.e., a region where it exceeds 30%). By containing C at 0.5% in a region where the Ge composition is 40% to 50%, the strain amounts can be reduced by about 12% and 10%, respectively, while Ev is not substantially changed. It is possible to reduce a threshold value and to increase a driving current while ensuring a large critical thickness of the SiGe channel layer.

Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and Sic microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

Abstract: After the surface of a Si substrate 1 has been pretreated, an SiGeC layer 2 is formed on the Si substrate 1 using an ultrahigh vacuum chemical vapor deposition (UHV-CVD) apparatus. During this process step, the growth temperature of the SiGeC layer 2 is set at 490° C. or less and Si2H6, GeH4 and SiH3CH3 are used as Si, Ge and C sources, respectively, whereby the SiGeC layer 2 with good crystallinity can be formed.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: An initial estimated value of a process condition is set, and a structure of an element of a semiconductor device is estimated by a process simulator, after which an estimated value of a physical amount measurement value is calculated. Then, an actual measurement value of a physical amount of the element of the semiconductor device, which is obtained by an optical evaluation method, and a theoretical calculated value thereof are compared with each other, so as to obtain a probable structure of the measured semiconductor device element by using, for example, a simulated annealing, or the like. A process condition in a process for other semiconductor device elements can be corrected by using the results.

Abstract: A Si1−xGex/Si1−yCy short-period superlattice which functions as a single SiGeC layer is formed by alternately growing Si1−xGex layers (0<x<1) and Si1−yCy layers (0<y<1) each having a thickness corresponding to several atomic layers which is small enough to prevent discrete quantization levels from being generated. This provides a SiGeC mixed crystal which is free from Ge—C bonds and has good crystalline quality and thermal stability. The Si1−xGex/Si1−yCy short-period superlattice is fabricated by a method in which Si1−xGex layers and Si1−yCy layers are epitaxially grown alternately, or a method in which a Si/Si1−xGex short-period superlattice is first formed and then C ions are implanted into the superlattice followed by annealing for allowing implanted C ions to migrate to Si layers.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: A crystal growing apparatus comprises a vacuum vessel, a heating lamp, a lamp controller for controlling the heating lamp, a gas inlet port, a flow rate adjuster for adjusting the flow rate of a gas, a pyrometer for measuring the temperature of a substrate, and a gas supply unit for supplying a Si2H6 gas or the like to the vacuum vessel. An apparatus for ellipsometric measurement comprises: a light source, a polariscope, a modulator, an analyzer, a spectroscope/detector unit, and an analysis control unit for calculating &PSgr;, &Dgr;. In removing a chemical oxide film on the substrate therefrom, in-situ ellipsometric measurement allows a discrimination between a phase 1 during which a surface of the substrate is covered with the oxide film and a phase 2 during which the surface of the substrate is partially exposed so that the supply of gas suitable for the individual phases is performed and halted.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: A semiconductor light-emitting device with a double hetero structure, including: an active layer made of Ga.sub.1-x In.sub.x N (0.ltoreq.x.ltoreq.0.3) doped with a p-type impurity and an n-type impurity; and first and second cladding layers provided so as to sandwich the active layer.

Abstract: A semiconductor light-emitting device with a double hetero structure, including: an active layer made of Ga.sub.1-x In.sub.x N (0.ltoreq.x.ltoreq.0.3) doped with a p-type impurity and an n-type impurity; and first and second cladding layers provided so as to sandwich the active layer.

Abstract: A semiconductor light-emitting device with a double hetero structure, including: an active layer made of Ga.sub.1-x In.sub.x N (0.ltoreq.x.ltoreq.0.3) doped with a p-type impurity and an n-type impurity; and first and second cladding layers provided so as to sandwich the active layer.

Abstract: A first insulating film is formed on a semiconductor substrate. A metal wire made of an aluminum alloy containing copper is formed on the first insulating film. An antireflection film is formed on the top face of the metal wire. On the region of the side face of the metal wire uncovered with an aluminum oxide film, there is formed a copper sulfide film, which is a sulfide film of copper. A second insulating film is formed over the metal wire formed with the antireflection film as well as the copper sulfide film and the first insulating film.