Abstract: An oven-controlled crystal oscillator according to one or more embodiments may include a core section having a crystal resonator, an oscillator IC and a heating IC, wherein the core section is supported by a package via an interposer, and furthermore the core section is hermetically encapsulated in the package.

Abstract: A novel therapeutic drug for malignant tumors, cancer stem cells, or fibrosis is obtained. A therapeutic drug for malignant tumors or cancer stem cells is used that includes at least one compound selected from the group consisting of compounds represented by formulas (1), (2), and (5), a salt thereof, or a solvate thereof. Alternatively, a therapeutic drug for fibrosis can be used that includes at least one compound selected from the group consisting of compounds represented by formulas (1), (2), and (5), a salt thereof, or a solvate thereof.

Abstract: A novel therapeutic drug for malignant tumors, cancer stem cells, or fibrosis is obtained. A therapeutic drug for malignant tumors or cancer stem cells is used that includes at least one compound selected from the group consisting of compounds represented by formulas (1), (2), and (5), a salt thereof, or a solvate thereof. Alternatively, a therapeutic drug for fibrosis can be used that includes at least one compound selected from the group consisting of compounds represented by formulas (1), (2), and (5), a salt thereof, or a solvate thereof.

Abstract: To obtain a novel therapeutic drug for a malignant tumor or fibrosis. Used is a compound represented by formula (1), a salt thereof, or a solvate thereof. Also used is a therapeutic drug for a malignant tumor or a therapeutic drug for fibrosis, comprising a compound represented by formula (1), a salt thereof, or a solvate thereof.

Abstract: To obtain a novel therapeutic drug for a malignant tumor or fibrosis. Used is a compound represented by formula (1), a salt thereof, or a solvate thereof. Also used is a therapeutic drug for a malignant tumor or a therapeutic drug for fibrosis, comprising a compound represented by formula (1), a salt thereof, or a solvate thereof.

Abstract: A novel therapeutic drug for malignant tumors, cancer stem cells, or fibrosis is obtained. A therapeutic drug for malignant tumors or cancer stem cells is used that includes at least one compound selected from the group consisting of compounds represented by formulas (1), (2), and (5), a salt thereof, or a solvate thereof. Alternatively, a therapeutic drug for fibrosis can be used that includes at least one compound selected from the group consisting of compounds represented by formulas (1), (2), and (5), a salt thereof, or a solvate thereof.

Abstract: The invention relates to low-molecular-weight compounds which are capable of inducing differentiation of mesenchymal stem cell into hepatocytes.

Abstract: The purpose is to select low-molecular-weight compounds which are effective in inducing differentiation of mesenchymal stem cell into hepatocyte and to develop a safe differentiation-inducing method having excellent efficiency of differentiating mesenchymal stem cell into hepatocyte. Provided are at least one compound selected from the group consisting of compounds represented by formulae (1) and (2), a salt thereof, or a solvate of them; a differentiation inducer comprising at least one compound selected from the group consisting of compounds represented by formulae (1) and (2), a salt thereof, or a solvate of them; and a differentiation inducer comprising a compound represented by formula (8), a salt thereof, or a solvate of them.

Abstract: An insole easy to wash and excellent in adhesiveness to the sole of a shoe is provided. An insole produced by punching a piece of the shape of a sole of a shoe or the shape of the leading terminal of a sole of a shoe out of a thermoplastic elastomer by the injection molding technique.

Abstract: There is provided a method of controlling direct memory access for a digital signal-processing system. Direct memory access (DMA) instructions for executing data transfer by direct memory access between a data memory storing data and an external device are provided in a program, together with arithmetic processing instructions for executing arithmetic processing. The data transfer by the direct memory access is executed between the data memory and the external device according to each of the DMA instructions which has been decoded during execution of the program, upon decoding thereof. There is also provided a digital signal-processing system which causes data transfer by direct memory access to begin. An arithmetic operation device of the system arithmetically processes data read out from a data memory of the same under the control of decoded instructions of a program.

Abstract: A method of filling a polygonal region enables a polygon of any shape to be filled with pixels with a simple algorithm. A display memory area and a working area each having a plurality of addresses correponding to all the pixels on a display screen are provided. A minimum rectangular area including the polygon is determined in accordance with all the polygon vertices, and the minimum rectangular area within the working area is cleared. A straight line (or an edge) connecting each pair of adjoining vertices of the polygon is described to the display memory area with predetermined values. The edges are also described to the working area but in accordance with three rules. Under Rule 1, when a constituent dot of the edge is described to the corresponding address, the data in the address is inverted. Under Rule 2, a start constituent dot of each edge is described only when the edge to be described has an inclination different in polarity from the precedingly described edge.

Abstract: A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area.

Abstract: A video display control system for displaying a video image on a screen of a video display unit. This video display control system basically comprises a VRAM (video RAM) and a video display processor (VDP). The VRAM has memory locations corresponding to display elements on the screen. The VDP includes a first register for receiving area information identifying a display area on the screen, an address generator for generating addresses of memory locations corresponding to the display area in accordance with the area information, and a memory accessing circuit for accessing the memory locations having the addresses. Therefore, the memory accessing operation through this VDP does not need a complicated support by a central processing unit. The VDP further comprises a second register for storing a color code supplied from an external device or read from the VRAM.

Abstract: A video display control system comprises a video display processor (VDP) which is capable of accessing to a video RAM (VRAM) at an extremely high-speed. The VRAM used in this system comprises first and second dynamic RAMs each having an address input terminal to which row address data and column address data are supplied, a row address strobe input terminal, a column address strobe input terminal, and a data input/output terminal. The row address data is latched at the leading edge of a row address strobe signal applied to the row address strobe input terminal, while the column address data is latched at the leading edge of a column address strobe signal applied to the column address strobe input terminal. An access to an address of each dynamic RAM is established when both of the row and column address data are latched. The VDP comprises a VRAM interface for controlling an access to the first and second dynamic RAMs which is connected to the RAMs through a common address bus.