Patents by Inventor Minoru Yamagami
Minoru Yamagami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9520176Abstract: A semiconductor apparatus disclosed in this disclosure includes a first channel formed in a first area and including a first power supply pad, a first clock pad, a first command address pad, a first data input/output pad and a first memory cell array; a second channel formed in a second area and including a second power supply pad, a second clock pad, a second command address pad, a second data input/output pad and a second memory cell array, the first and second channels being independently controllable from each other; and mesh structure lines straddling the first area and second area and connected to the first and second power supply pads.Type: GrantFiled: April 20, 2015Date of Patent: December 13, 2016Assignee: Micron Technology, Inc.Inventor: Minoru Yamagami
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Publication number: 20150310907Abstract: A semiconductor apparatus disclosed in this disclosure includes a first channel formed in a first area and including a first power supply pad, a first clock pad, a first command address pad, a first data input/output pad and a first memory cell array; a second channel formed in a second area and including a second power supply pad, a second clock pad, a second command address pad, a second data input/output pad and a second memory cell array, the first and second channels being independently controllable from each other; and mesh structure lines straddling the first area and second area and connected to the first and second power supply pads.Type: ApplicationFiled: April 20, 2015Publication date: October 29, 2015Inventor: Minoru YAMAGAMI
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Patent number: 8830773Abstract: Disclosed herein is a device that includes: first and second memory mats each including a plurality of bit lines; a sense area arranged between the first and second memory mats; a column selection line provided on the first memory mat; and a compensation capacitance provided on the second memory mat. The sense area includes a plurality of sense amplifiers. Each of the sense amplifiers is connected to an associated one or ones of the bit lines. At least one of the sense amplifiers is selected based on a column selection signal supplied via the column selection line. At least a part of the compensation capacitance is formed in a same wiring layer as the column selection line.Type: GrantFiled: March 13, 2012Date of Patent: September 9, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Minoru Yamagami, Hisayuki Nagamine
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Patent number: 8767484Abstract: A semiconductor device comprises a first region and a second region. The first region includes a plurality of memory cells each of which holds respective data and a plurality of sense amplifiers that respectively amplify the data in the plurality of memory cells, based on a first voltage. The second region is provided along one side of the first region and includes a first power supply generation circuit that generates the first voltage, based on a second voltage. The second voltage being supplied to the first power supply circuit by a first power supply interconnect extends on the first region in a first direction parallel to the one side of the first region.Type: GrantFiled: June 6, 2012Date of Patent: July 1, 2014Inventors: Minoru Yamagami, Hisayuki Nagamine
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Patent number: 8704223Abstract: A transistor of a characteristic checking element has a gate electrode connected to a measurement pad disposed in a dicing line and to an internal measurement pad disposed inside a semiconductor device. In a P/W process, a gate insulating film of the transistor is broken by an electric voltage applied via the internal measurement pad. Since the gate insulating film of the transistor is broken, a new current path is formed. Thus, measurement of accurate characteristics of the characteristic checking element is inhibited.Type: GrantFiled: January 8, 2008Date of Patent: April 22, 2014Inventors: Minoru Yamagami, Hisayuki Nagamine
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Publication number: 20120314471Abstract: A semiconductor device comprises a first region and a second region. The first region includes a plurality of memory cells each of which holds respective data and a plurality of sense amplifiers that respectively amplify the data in the plurality of memory cells, based on a first voltage. The second region is provided along one side of the first region and includes a first power supply generation circuit that generates the first voltage, based on a second voltage. The second voltage being supplied to the first power supply circuit by a first power supply interconnect extends on the first region in a first direction parallel to the one side of the first region.Type: ApplicationFiled: June 6, 2012Publication date: December 13, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Minoru YAMAGAMI, Hisayuki NAGAMINE
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Publication number: 20120236669Abstract: Disclosed herein is a device that includes: first and second memory mats each including a plurality of bit lines; a sense area arranged between the first and second memory mats; a column selection line provided on the first memory mat; and a compensation capacitance provided on the second memory mat. The sense area includes a plurality of sense amplifiers. Each of the sense amplifiers is connected to an associated one or ones of the bit lines. At least one of the sense amplifiers is selected based on a column selection signal supplied via the column selection line. At least a part of the compensation capacitance is formed in a same wiring layer as the column selection line.Type: ApplicationFiled: March 13, 2012Publication date: September 20, 2012Applicant: Elpida Memory, Inc.Inventors: Minoru YAMAGAMI, Hisayuki Nagamine
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Patent number: 8063661Abstract: To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area.Type: GrantFiled: June 22, 2010Date of Patent: November 22, 2011Assignee: Elpida Memory, Inc.Inventors: Takashi Ishihara, Minoru Yamagami, Hisayuki Nagamine
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Publication number: 20100327966Abstract: To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area.Type: ApplicationFiled: June 22, 2010Publication date: December 30, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Takashi ISHIHARA, Minoru YAMAGAMI, Hisayuki NAGAMINE
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Patent number: 7508238Abstract: A semiconductor integrated circuit device includes a main region on which a main circuit is formed and a spare cell region for logic modification of the circuit formed on the main region. The spare cell region includes a P-channel transistor region, an N-channel transistor region, a plurality of gate electrodes provided above the P-channel transistor region and the N-channel transistor region, a main wire layer that is a different layer from the gate electrodes, and a plurality of bypass wires that are formed at a different layer from the main wire layer. Each of the plurality of bypass wires has a structure that can be connected to the main wire layer at more than one point through contact holes formed in a dielectric layer intervening between the main wire layer and the bypass wires.Type: GrantFiled: August 2, 2005Date of Patent: March 24, 2009Assignee: Elpida Memory, Inc.Inventor: Minoru Yamagami
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Patent number: 7432391Abstract: The present invention is to provide a safe process for the production of tert-butyl N-(2-bromoethyl)carbamate where operation is simple, handling of the final product is easy, working efficiency is good and yield is high. A process for the production of tert-butyl N-(2-bromoethyl)carbamate, characterized in that, 2-bromoethylamine or a salt thereof is made to react with an agent for introducing a tert-butoxy carbonyl group in a water-soluble solvent in the presence of sodium hydroxide and then water as a crystallizing solvent and seed crystals are added to the reaction solution whereby crystals of tert-butyl N-(2-bromoethyl)carbamate are separated out therefrom.Type: GrantFiled: May 24, 2005Date of Patent: October 7, 2008Assignee: Daito Chemix CorporationInventors: Makoto Momomoto, Yoshiaki Suzuki, Minoru Yamagami, Keisuke Matsumoto, Yusuke Sakaguchi
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Publication number: 20080169467Abstract: A transistor of a characteristic checking element has a gate electrode connected to a measurement pad disposed in a dicing line and to an internal measurement pad disposed inside a semiconductor device. In a P/W process, a gate insulating film of the transistor is broken by an electric voltage applied via the internal measurement pad. Since the gate insulating film of the transistor is broken, a new current path is formed. Thus, measurement of accurate characteristics of the characteristic checking element is inhibited.Type: ApplicationFiled: January 8, 2008Publication date: July 17, 2008Inventors: Minoru Yamagami, Hisayuki Nagamine
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Publication number: 20080139839Abstract: The present invention is to provide a safe process for the production of tert-butyl N-(2-bromoethyl)carbamate where operation is simple, handling of the final product is easy, working efficiency is good and yield is high. A process for the production of tert-butyl N-(2-bromoethyl)carbamate, characterized in that, 2-bromoethylamine or a salt thereof is made to react with an agent for introducing a tert-butoxy carbonyl group in a water-soluble solvent in the presence of sodium hydroxide and then water as a crystallizing solvent and seed crystals are added to the reaction solution whereby crystals of tert-butyl N-(2-bromoethyl)carbamate are separated out therefrom.Type: ApplicationFiled: May 24, 2005Publication date: June 12, 2008Inventors: Makoto Momomoto, Yoshiaki Suzuki, Minoru Yamagami, Keisuke Matsumoto, Yusuke Sakaguchi
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Publication number: 20060027835Abstract: A semiconductor integrated circuit device includes a main region on which a main circuit is formed and a spare cell region for logic modification of the circuit formed on the main region. The spare cell region includes a P-channel transistor region, an N-channel transistor region, a plurality of gate electrodes provided above the P-channel transistor region and the N-channel transistor region, a main wire layer that is a different layer from the gate electrodes, and a plurality of bypass wires that are formed at a different layer from the main wire layer. Each of the plurality of bypass wires has a structure that can be connected to the main wire layer at more than one point through contact holes formed in a dielectric layer intervening between the main wire layer and the bypass wires.Type: ApplicationFiled: August 2, 2005Publication date: February 9, 2006Inventor: Minoru Yamagami
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Patent number: 6346820Abstract: In a characteristics evaluation circuit incorporated into a semiconductor wafer, a dummy element is connected to at least two pads, and a depletion type MOS transistor is connected between the pads. A fuse is connected to a gate of the depletion type MOS transistor, and a gate voltage control pad is connected to the fuse.Type: GrantFiled: June 1, 2000Date of Patent: February 12, 2002Assignee: NEC CorporationInventor: Minoru Yamagami