Patents by Inventor Min Su Choi
Min Su Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240163139Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.Type: ApplicationFiled: November 10, 2023Publication date: May 16, 2024Applicant: Electronics and Telecommunications Research InstituteInventors: Young-deuk JEON, Young-Su KWON, Yi-Gyeong KIM, Su-Jin PARK, Min-Hyung CHO, Jae-Woong CHOI
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Publication number: 20240162113Abstract: In one example, an electronic device comprises a substrate comprising a conductive structure and an inner side and an outer side, a first electronic component over the inner side of the substrate and coupled with the conductive structure, a lid over the substrate and the first electronic component and comprising a first hole in the lid, and a thermal interface material between the first electronic component and the lid. The thermal interface material is in the first hole. Other examples and related methods are also disclosed herein.Type: ApplicationFiled: November 11, 2022Publication date: May 16, 2024Applicants: Amkor Technology Singapore Holding Pte. Ltd., Amkor Technology Singapore Holding Pte. Ltd.Inventors: Dong Hyeon Park, Yun Ah Kim, Seok Ho Na, Won Ho Choi, Dong Su Ryu, Jo Hyun Bae, Min Jae Kong, Jin Young Khim, Jae Yeong Bae, Dong Hee Kang
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Publication number: 20240128517Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.Type: ApplicationFiled: January 19, 2022Publication date: April 18, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Hae-Jin LIM, Jin-Hak KONG, Soon-O LEE, Kyu-Hyun CHOI, Do-Gyun KIM, Su-Ji CHOI, Kwang-Su HWANGBO, Geon-Woo MIN, Min-Ki JO, Jae-Won LIM, Hak-Kyun KIM, Je-Jun LEE, Ji-Min JUNG, Jae-Woong KIM, Jong-Sik PARK, Yu-Sung CHOE, Byoung-Gu LEE, Duk-Hyun RYU, Kwan-Hee LEE, Jae-Eun LEE, Bo-Hyun KANG, Pil-Kyu PARK
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Publication number: 20240128605Abstract: Provided are an electrode assembly, a battery, and a battery pack and vehicle including the same. An electrode assembly, in which a first electrode, a second electrode, and a separator interposed therebetween are wound about an axis to define a core and an outer circumferential surface. At least one of the first electrode and the second electrode includes, at a long side end portion, an uncoated portion exposed beyond the separator in a direction of the axis. At least a part of the uncoated portion is bent in a radial direction of the electrode assembly to define a bent surface region having overlapping layers of the uncoated portion. The bent surface region includes a welding target region having a number of the overlapping layers of the uncoated portion, and the welding target region extends along a radial direction of the electrode assembly.Type: ApplicationFiled: February 18, 2022Publication date: April 18, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Min-Woo KIM, Do-Gyun KIM, Kyung-Wook CHO, Geon-Woo MIN, Min-Ki JO, Jae-Woong KIM, Kwang-Su HWANGBO, Hae-Jin LIM, Su-Ji CHOI, Jae-Won LIM, Hak-Kyun KIM, Je-Jun LEE, Ji-Min JUNG
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Publication number: 20240121809Abstract: A method of a first terminal may include: identifying first RB set(s) to be used for SL communication among consecutive RB sets through an LBT procedure; identifying a first subchannel group included in the first RB set(s) and a second subchannel group including a first PRB in the first RB set(s), the first PRB being not included in the first subchannel group; configuring the first PRB within the second subchannel group as an SL communication resource; and transmitting, to a second terminal, control information indicating that the first PRB is configured as the SL communication resource.Type: ApplicationFiled: September 27, 2023Publication date: April 11, 2024Inventors: Jun Hyeong KIM, Go San NOH, Il Gyu KIM, Man Ho PARK, Nak Woon SUNG, Jae Su SONG, Nam Suk LEE, Hee Sang CHUNG, Min Suk CHOI
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Patent number: 11410026Abstract: Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.Type: GrantFiled: November 15, 2018Date of Patent: August 9, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo-Yeong Cho, Seong-Il O, Hak-Soo Yu, Min-Su Choi
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Publication number: 20220214749Abstract: A haptic effect transmission method for providing real-time immersive content according to the present invention includes executing participatory content in which one or more users participate, collecting motion information of the users participating in the participatory content through a haptic device, multiplexing the motion information with video and audio files of the participatory content to obtain a multiplexed file, and demultiplexing the multiplexed file and providing the demultiplexed file to a display device and a haptic device of a client terminal.Type: ApplicationFiled: September 18, 2019Publication date: July 7, 2022Inventors: Woo Chool PARK, Jun Hwan JANG, Yong Hwa KIM, Jin Wook YANG, Sang Pil YOON, Hyun Wook KIM, Eun Kyung CHO, Min Su CHOI, Jun Suk LEE, Jae Young YANG
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Patent number: 11043397Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.Type: GrantFiled: July 12, 2019Date of Patent: June 22, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myeong-Dong Lee, Min-Su Choi, Jun-Hyeok Ahn, Sung-Hee Han, Ce-Ra Hong
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Publication number: 20200219732Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.Type: ApplicationFiled: July 12, 2019Publication date: July 9, 2020Inventors: Myeong-Dong LEE, Min-Su CHOI, Jun-Hyeok AHN, Sung-Hee HAN, Ce-Ra HONG
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Publication number: 20190318230Abstract: Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.Type: ApplicationFiled: November 15, 2018Publication date: October 17, 2019Inventors: WOO-YEONG CHO, SEONG-IL O, HAK-SOO YU, MIN-SU CHOI
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Publication number: 20190214293Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a cell region and a peripheral region having different active region densities, forming cell trenches for limiting cell active regions in the cell region so that the cell active regions are formed to be spaced apart by a first width in a first direction and by a second width in a second direction, forming peripheral trenches for limiting a peripheral active region in the peripheral region, and forming, in the cell trenches, a first insulating layer continuously extending in the first and second directions and contacting sidewalls of the cell active regions, and having a thickness equal to or greater than half of the first width and less than half of the second width.Type: ApplicationFiled: July 6, 2018Publication date: July 11, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kyu Jin Kim, Min Su Choi, Sung Hee Han, Bong Soo Kim, Yoo Sang Hwang
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Patent number: 10337391Abstract: A device for cooling and heating a urea solution to be injected into exhaust gas discharged from an engine in order to reduce nitrogen oxides in the exhaust gas includes an engine including a cooling fan, a coolant pump, and a main cooler; a urea solution tank storing the urea solution and having an embedded heat exchange pipe through which first coolant and second coolant circulates; an additional coolant tank storing the second coolant; a water pump supplying the second coolant from the additional coolant tank to the heat exchange pipe; a valve configured to be opened or closed in order to supply the first coolant and the second coolant to the heat exchange pipe through a supply line, and to move the first coolant and the second coolant, which are discharged from the heat exchange pipe through a discharge line, to rise coolant pump and the additional coolant tank, respectively and a controller for supplying the second coolant to the heat exchange pipe through the supply line when the urea solution temperatuType: GrantFiled: July 29, 2015Date of Patent: July 2, 2019Assignee: Volvo Construction Equipment ABInventors: Dong-Myoung Choi, Yu-Hee Lee, Eun-Geon Yuk, Sung-Hwan Shin, Min-Su Choi
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Patent number: 10199379Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.Type: GrantFiled: December 7, 2017Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
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Publication number: 20180209325Abstract: A device for cooling and heating a urea solution to be injected into exhaust gas discharged from an engine in order to reduce nitrogen oxides in the exhaust gas includes an engine including a cooling fan, a coolant pump, and a main cooler; a urea solution tank storing the urea solution and having an embedded heat exchange pipe through which first coolant and second coolant circulates; an additional coolant tank storing the second coolant; a water pump supplying the second coolant from the additional coolant tank to the heat exchange pipe; a valve configured to be opened or closed in order to supply the first coolant and the second coolant to the heat exchange pipe through a supply line, and to move the first coolant and the second coolant, which are discharged from the heat exchange pipe through a discharge line, to rise coolant pump and the additional coolant tank, respectively and a controller for supplying the second coolant to the heat exchange pipe through the supply line when the urea solution temperatuType: ApplicationFiled: July 29, 2015Publication date: July 26, 2018Applicant: VOLVO CONSTRUCTION EQUIPMENT ABInventors: Dong-Myoung CHOI, Yu-Hee LEE, Eun-Geon YUK, Sung-Hwan SHIN, Min-Su CHOI
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Publication number: 20180108662Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.Type: ApplicationFiled: December 7, 2017Publication date: April 19, 2018Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
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Patent number: 9853031Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.Type: GrantFiled: February 15, 2017Date of Patent: December 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
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Patent number: 9634012Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.Type: GrantFiled: February 4, 2016Date of Patent: April 25, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
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Patent number: D1016029Type: GrantFiled: August 22, 2022Date of Patent: February 27, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Young Lee, Hyok-Su Choi, Chung-Ha Kim, Jong-Bo Jung, Min-Young Park
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Patent number: D1016030Type: GrantFiled: August 22, 2022Date of Patent: February 27, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Young Lee, Hyok-Su Choi, Chung-Ha Kim, Jong-Bo Jung, Min-Young Park
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Patent number: D1016775Type: GrantFiled: May 4, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Young Lee, Hyok-Su Choi, Chung-Ha Kim, Jong-Bo Jung, Min-Young Park