Patents by Inventor Mircea R. Stan
Mircea R. Stan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11451261Abstract: Asynchronous stream generation and processing techniques are described that support implementation of an asynchronous stream mote in which one or more analog sensor signals are used to generate one or more asynchronous streams. On-device operations processing of the one or more asynchronous streams may be performed before transmission of the result(s) to other system components (e.g., peer motes or higher-level system components).Type: GrantFiled: July 24, 2020Date of Patent: September 20, 2022Assignee: University of Virginia Patent FoundationInventors: Mircea R. Stan, Luisa P. Gonzalez Guerrero
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Patent number: 11436401Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.Type: GrantFiled: September 16, 2019Date of Patent: September 6, 2022Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATIONInventors: Ke Wang, Kevin Skadron, Mircea R. Stan, Runjie Zhang
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Patent number: 11049551Abstract: A method of processing data in a memory can include accessing an array of memory cells located on a semiconductor memory die to provide a row of data including n bits, latching the n bits in one or more row buffer circuits adjacent to the array of memory cells on the semiconductor memory die to provide latched n bits operatively coupled to a column address selection circuit on the semiconductor memory die to provide a portion of the n latched bits as data output from the semiconductor memory die responsive to a memory read operation, and serially transferring the latched n bits in the row buffer circuit to an arithmetic logic unit (ALU) circuit located adjacent to the row buffer circuit on the semiconductor memory die.Type: GrantFiled: November 13, 2019Date of Patent: June 29, 2021Assignee: University of Virginia Patent FoundationInventors: Marzieh Lenjani, Patricia Gonzalez, Mircea R. Stan, Kevin Skadron
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Publication number: 20210142846Abstract: A method of processing data in a memory can include accessing an array of memory cells located on a semiconductor memory die to provide a row of data including n bits, latching the n bits in one or more row buffer circuits adjacent to the array of memory cells on the semiconductor memory die to provide latched n bits operatively coupled to a column address selection circuit on the semiconductor memory die to provide a portion of the n latched bits as data output from the semiconductor memory die responsive to a memory read operation, and serially transferring the latched n bits in the row buffer circuit to an arithmetic logic unit (ALU) circuit located adjacent to the row buffer circuit on the semiconductor memory die.Type: ApplicationFiled: November 13, 2019Publication date: May 13, 2021Inventors: Marzieh Lenjani, Patricia Gonzalez, Mircea R. Stan, Kevin Skadron
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Publication number: 20210028818Abstract: Asynchronous stream generation and processing techniques are described that support implementation of an asynchronous stream mote in which one or more analog sensor signals are used to generate one or more asynchronous streams. On-device operations processing of the one or more asynchronous streams may be performed before transmission of the result(s) to other system components (e.g., peer motes or higher-level system components).Type: ApplicationFiled: July 24, 2020Publication date: January 28, 2021Inventors: Mircea R. Stan, Luisa P. Gonzalez Guerrero
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Publication number: 20200151380Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.Type: ApplicationFiled: September 16, 2019Publication date: May 14, 2020Applicant: UNIVERSITY OF VIRGIINIA PATENT FOUNDATIONInventors: Ke Wang, Kevin Skadron, Mircea R. Stan, Runjie Zhang
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Patent number: 10482210Abstract: A virtual force controlled collapse chip connection (C4) pad placement optimization frame-work for 2D power delivery grids is proposed. The present optimization framework regards power pads as mobile “positive charged particles” and current resources as a “negative charged back-ground.” The virtual electrostatic force is calculated from voltage gradients. This optimization framework optimizes pad locations by moving pads according to the virtual forces exerted on them by other pads and current sources in the system. Within this framework, three algorithms are proposed to meet various requirements of optimization quality and speed. These algorithms minimize resistive voltage drop (IR drop), the maximum current density, and power distribution network metal power dissipation at the same time.Type: GrantFiled: January 19, 2016Date of Patent: November 19, 2019Assignee: University of Virginia Patent FoundationInventors: Ke Wang, Kevin Skadron, Mircea R. Stan, Runjie Zhang, Brett Meyer
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Patent number: 10417367Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.Type: GrantFiled: June 1, 2015Date of Patent: September 17, 2019Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATIONInventors: Ke Wang, Kevin Skadron, Mircea R. Stan, Runjie Zhang
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Publication number: 20160210392Abstract: A virtual force controlled collapse chip connection (C4) pad placement optimization frame-work for 2D power delivery grids is proposed. The present optimization framework regards power pads as mobile “positive charged particles” and current resources as a “negative charged back-ground.” The virtual electrostatic force is calculated from voltage gradients. This optimization framework optimizes pad locations by moving pads according to the virtual forces exerted on them by other pads and current sources in the system. Within this framework, three algorithms are proposed to meet various requirements of optimization quality and speed. These algorithms minimize resistive voltage drop (IR drop), the maximum current density, and power distribution network metal power dissipation at the same time.Type: ApplicationFiled: January 19, 2016Publication date: July 21, 2016Inventors: Ke Wang, Kevin Skadron, Mircea R. Stan, Runjie Zhang, Brett Meyer
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Publication number: 20150370944Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.Type: ApplicationFiled: June 1, 2015Publication date: December 24, 2015Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATIONInventors: Ke Wang, Kevin Skadron, Mircea R. Stan, Runjie Zhang
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Patent number: 8953366Abstract: The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it.Type: GrantFiled: May 11, 2011Date of Patent: February 10, 2015Assignee: University of Virginia Patent FoundationInventors: Stuart A. Wolf, Jiwei Lu, Mircea R. Stan
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Publication number: 20130058157Abstract: The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it.Type: ApplicationFiled: May 11, 2011Publication date: March 7, 2013Applicant: University of Virginia Patent Foundation, d/b/a University of Virginia Licensing & Ventures GroupInventors: Stuart A. Wolf, Jiwei Lu, Mircea R. Stan
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Patent number: 8000161Abstract: A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory.Type: GrantFiled: June 30, 2008Date of Patent: August 16, 2011Assignee: University of Virginia Patent FoundationInventors: Mircea R. Stan, Adam C. Cabe
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Publication number: 20090174435Abstract: The invention discloses new and advantageous uses for carbon/graphene nanoribbons (GNRs), which includes, but is not limited to, electronic components for integrated circuits such as NOT gates, OR gates, AND gates, nano-capacitors, and other transistors. More specifically, the manipulation of the shapes, sizes, patterns, and edges, including doping profiles, of GNRs to optimize their use in various electronic devices is disclosed.Type: ApplicationFiled: October 1, 2008Publication date: July 9, 2009Applicant: University of VirginiaInventors: Mircea R. Stan, Avik Ghosh
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Publication number: 20090003040Abstract: A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory.Type: ApplicationFiled: June 30, 2008Publication date: January 1, 2009Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATIONInventors: Mircea R. Stan, Adam C. Cabe
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Patent number: 7397395Abstract: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.Type: GrantFiled: February 16, 2005Date of Patent: July 8, 2008Assignee: Intel CorporationInventors: James W Tschanz, Mircea R. Stan, Muhammad M Khellah, Yibin Ye, Vivek K De
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Patent number: 6917237Abstract: Embodiments circuits provide a transistor body bias voltage so that the ratio of ION to IOFF is constant over a range of temperature, where ION is a transistor current when ON and IOFF is a (leakage) transistor current when OFF. In one embodiment, a nFET is biased to provide ION to a current mirror that sources a current AION to a node, a nFET is biased to provide IOFF to a current mirror that sinks a current BIOFF from the node, and an amplifier provides feedback from the node to the body terminals of the nFETs so that at steady state AION=BIOFF, where A and B are constants independent over a range of temperature. In this way, the ratio ION/IOFF is maintained at B/A for some range of temperatures. Other embodiments are described and claimed.Type: GrantFiled: March 2, 2004Date of Patent: July 12, 2005Assignee: Intel CorporationInventors: James W. Tschanz, Mircea R. Stan, Siva G. Narendra, Vivek K. De
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Patent number: 6710627Abstract: A technique to individually adjust noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network includes identifying precharge nodes of the dynamic circuit that require a reduction of noise. The technique further includes identifying NMOS transistor drains connected to respective precharge nodes, and creating a pull-up network of PMOS transistors for the identified precharge nodes. After creating a pull-up network of PMOS transistors, the technique includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve noise immunity and performance of the dynamic circuit. After arranging the order of the PMOS transistors, the technique can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes.Type: GrantFiled: December 18, 2002Date of Patent: March 23, 2004Assignee: Intel CorporationInventors: Mircea R. Stan, Vivek K. De
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Publication number: 20030122580Abstract: A technique to individually adjust noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network includes identifying precharge nodes of the dynamic circuit that require a reduction of noise. The technique further includes identifying NMOS transistor drains connected to respective precharge nodes, and creating a pull-up network of PMOS transistors for the identified precharge nodes. After creating a pull-up network of PMOS transistors, the technique includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve noise immunity and performance of the dynamic circuit. After arranging the order of the PMOS transistors, the technique can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes.Type: ApplicationFiled: December 18, 2002Publication date: July 3, 2003Applicant: Intel CorporationInventors: Mircea R. Stan, Vivek K. De
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Patent number: 6518796Abstract: A system of individually adjusting noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network comprises identifying precharge nodes of the dynamic circuit requiring a reduction of noise. Then further identifying NMOS transistor drains connected to the respective precharge nodes, then creating a pull-up network of PMOS transistors for the precharge nodes, respectively. After creating a pull-up network of PMOS transistors, the system further includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve the noise immunity and performance of the dynamic circuit. After completing the arranging of the order of the PMOS transistors, the system can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes, respectively.Type: GrantFiled: June 30, 2000Date of Patent: February 11, 2003Assignee: Intel CorporationInventors: Mircea R. Stan, Vivek K. De