Abstract: A memory device and method use a low digit line pre-charge voltage. In one embodiment, a memory device uses sense amplifier nodes to provide a pre-charge supply voltage to the digit lines. By using a low pre-charge voltage, the memory device does not require boosted word line and isolation control voltages. P-sense amplifier circuitry of the memory device is activated prior to n-sense amplifier circuitry during sense operations.

Abstract: A chip's interface is selected by using a fuse option coupled between integrated circuitry on the chip and logic circuitry. Fuse options correspond to antifuses or fuses. In one embodiment, a plurality of fuse options are manufactured in an integrated circuit such that a fuse option is coupled between integrated circuitry on the chip and separate and complete logic circuitry for different logic types used to interface a chip. In another embodiment, only one type of logic circuitry is manufactured on a chip, such that the logic circuitry has both a pull-up and pull-down transistor. A fuse is coupled with a pull-up control circuit of the logic circuitry. When the fuse is blown, the output circuit corresponds to GTL-terminated logic circuitry, using only the pull-down transistor. In a further embodiment, an antifuse is coupled with the pull-up control circuit.

Abstract: A memory module, such as a SIMM or DIMM, is provided which incorporates error correction circuitry. The error correction circuitry identifies and corrects errors in communications between the memory module and an external processor. A reliable data processing system is also provided, incorporating the memory module comprising the error correction circuitry with a processor. The yield of manufactured chips is increased by presorting the memory chips which make up the memory module, such that a chip with one or more defective cells may be included in a memory module so long as no other chip has defective cells at the same location.

Abstract: A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.

Abstract: A 09/392153 substrate, such as flip-chip type semiconductor die, connected to an opposing substrate, such as a silicon wafer, printed circuit board, or other substrate, Each substrate has a plurality of conductive bumps on its facing surface wherein the conductive bumps on each substrate are the mirror-image of the other substrate. The substrates are attached to one another in a manner in which the conductive bumps on one substrate form an electrical contact with its respective conductive bumps on the opposing substrate without mechanical attachment.

Abstract: An apparatus and a method for connecting one substrate, such as a flip-chip type semiconductor die, to an opposing substrate, such as a silicon wafer, printed circuit board, or other substrate. Each substrate has a plurality of conductive bumps on its facing surface wherein the conductive bumps on each substrate are the mirror-image of the other substrate. The substrates are attached to one another in a manner in which the conductive bumps on one substrate form an electrical contact with its respective conductive bumps on the opposing substrate without mechanical attachment.

Abstract: An integrated circuit laser antifuse is described which has two physical states. In the first physical state the laser antifuse has to conductive plates electrically separated by a layer of dielectric material. In the second physical state the two conductive plates are electrically connected through the dielectric in response to an external radiation source, such as a laser.

Abstract: A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.

Abstract: A method for connecting one substrate, such as a flip-chip type semiconductor die, to an opposing substrate, such as a silicon wafer, printed circuit board, or other substrate. Each substrate has a plurality of conductive bumps on its facing surface wherein the conductive bumps on each substrate are the mirror-image of the other substrate. The substrates are attached to one another in a manner in which the conductive bumps on one substrate form an electrical contact with its respective conductive bumps on the opposing substrate without mechanical attachment.

Abstract: A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.

Abstract: A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and data input/output connections are distributed around the memory to increase speed. Multiplexed latch circuitry is provided which incorporates separate data paths for both data read and write operations.

Abstract: A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and reads from memory cells located in different memory banks. Error detection circuitry evaluates data read from different memory banks and determines if a defect is present in the memory cells. Different test patterns and techniques are described for identifying defective memories.

Abstract: A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and input/output connections are distributed around the memory to increase speed. Page access operations are controlled to allow either single or burst writes.

Abstract: A three dimensional ferroelectric memory device formed on a semiconductor substrate has insulative material formed between rows of conductors to reduce cross talk between the conductors. Access circuitry or other circuitry is formed beneath the three dimensional structure. Continuous conductors, or staggered vias provide for connection to conductors forming the memory cells. An access circuit is provided which eliminates the need for an access transistor for each memory cell by using a memory cell with a reference cell in combination with sensing circuitry. Read cycles are followed by write cycles and an equilibrate cycle to reverse the effects of destructive reads on the memory cells. Side by side memory structures provide the ability to access using either a folded or open bit line circuit.

Abstract: A random access memory circuit is described which uses single ferroelectric memory cells to store data. The ferroelectric memory cells can be selectively read using reference cells to generate a reference voltage which is compared to a voltage representative of data stored on the memory cell using a multiplexed sense amplifier. In using two ferroelectric reference cells in which one contains a logical 0 polarization, and the other contains a logical 1 polarization, a single-ended reference voltage can be generated on a reference bit line. A ferroelectric memory cell can then be read by comparing the voltage on its corresponding bit line to the reference bit line using the sense amplifier. The content of the memory cell being read and the content of the reference cells can be rewritten on the same clock cycles to save on access time.

Abstract: A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and reads from memory cells located in different memory banks. Error detection circuitry evaluates data read from different memory banks and determines if a defect is present in the memory cells. Different test patterns and techniques are described for identifying defective memories.

Abstract: A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.

Abstract: A three dimensional ferroelectric memory device formed on a semiconductor substrate has insulative material formed between rows of conductors to reduce cross talk between the conductors. Access circuitry or other circuitry is formed beneath the three dimensional structure. Continuous conductors, or staggered vias provide for connection to conductors forming the memory cells. An access circuit is provided which eliminates the need for an access transistor for each memory cell by using a memory cell with a reference cell in combination with sensing circuitry. Read cycles are followed by write cycles and an equilibrate cycle to reverse the effects of destructive reads on the memory cells. Side by side memory structures provide the ability to access using either a folded or open bit line circuit.

Abstract: A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and input/output connections are distributed around the memory to increase speed. Page access operations are controlled to allow either single or burst writes.

Abstract: A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and data input/output connections are distributed around the memory to increase speed. Multiplexed latch circuitry is provided which incorporates separate data paths for both data read and write operations.