Patents by Inventor Misel-Myrto Papadopoulou

Misel-Myrto Papadopoulou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11838126
    Abstract: Apparatuses, systems, and techniques to select fifth-generation (5G) new radio data. In at least one embodiment, a processor includes one or more circuits to select 5G new radio signal information in parallel.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 5, 2023
    Assignee: NVIDIA Corporation
    Inventors: Misel Myrto Papadopoulou, Timothy James Martin
  • Publication number: 20230103866
    Abstract: Apparatuses, systems, and techniques to select fifth-generation (5G) new radio data. In at least one embodiment, a processor includes one or more circuits to select 5G new radio signal information in parallel.
    Type: Application
    Filed: October 26, 2021
    Publication date: April 6, 2023
    Inventors: Misel Myrto Papadopoulou, Timothy James Martin
  • Publication number: 20230070361
    Abstract: Apparatuses, systems, and techniques to perform and facilitate an interface for multi-user and/or multi-cell physical layer (PHY) signal processing pipelines in a fifth generation (5G) new radio (NR) network. In at least one embodiment, a software interface facilitates scalable execution of multi-user and/or multi-cell information by a 5G-NR PHY software library implementing one or more signal processing pipelines.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 9, 2023
    Inventors: Misel Myrto Papadopoulou, James Hansen Delfeld, Harsha Deepak Banuli Nanje Gowda
  • Publication number: 20140101405
    Abstract: Methods and apparatuses are provided for avoiding cold translation lookaside buffer (TLB) misses in a computer system. A typical system is configured as a heterogeneous computing system having at least one central processing unit (CPU) and one or more graphic processing units (GPUs) that share a common memory address space. Each processing unit (CPU and GPU) has an independent TLB. When offloading a task from a particular CPU to a particular GPU, translation information is sent along with the task assignment. The translation information allows the GPU to load the address translation data into the TLB associated with the one or more GPUs prior to executing the task. Preloading the TLB of the GPUs reduces or avoids cold TLB misses that could otherwise occur without the benefits offered by the present disclosure.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Misel-Myrto Papadopoulou, Lisa R. Hsu, Andrew G. Kegel, Nuwan S. Jayasena, Bradford M. Beckmann, Steven K. Reinhardt