Abstract: Field-effect transistors (FETs) employing edge transistor current leakage suppression to reduce FET current leakage, and related methods, are disclosed. The FET includes a gate that includes extended-length edge gate regions overlapping semiconductor layer edges to form extended length edge conduction channels in edge transistors. In this manner, the threshold voltage of the edges transistors is increased, thus reducing current leakage of the edges transistors and overall current leakage of the FET. In another aspect, a body connection implant that is formed to short a source or drain region to a body of the FET is extended in length to form body connection implant regions underneath at least a portion of the edge gate regions. In this manner, the work functions of the edge gate regions are increased in voltage thus increasing the threshold voltage of the edge transistors and reducing current leakage of the edges transistors and the FET.

Abstract: An integrated device that includes a substrate, a circuit region located over the substrate, a design keep out region located over the substrate, and a periphery structure located over the substrate. The design keep out region laterally surrounds the circuit region. The periphery structure includes a first plurality of interconnects that laterally surrounds the design keep out region. The periphery structure is configured to operate as an electrical seal ring and a mechanical crack stop.

Abstract: Certain aspects of the present disclosure generally relate to a one-time programmable (OTP) device including an antifuse device. The antifuse device generally includes a first active region, a second active region, a channel region disposed between the first active region and the second active region, a gate region disposed above the channel region, and a first set of lightly doped drain (LDD) extension regions extending partially across the channel region from the first active region and the second active region and extending into a portion of the channel region underneath the gate region. The first set of LDD extension regions have a same dopant type as the gate region and at least one of the first active region or the second active region.

Abstract: Field-effect transistors (FETs) employing edge transistor current leakage suppression to reduce FET current leakage, and related methods, are disclosed. The FET includes a gate that includes extended-length edge gate regions overlapping semiconductor layer edges to form extended length edge conduction channels in edge transistors. In this manner, the threshold voltage of the edges transistors is increased, thus reducing current leakage of the edges transistors and overall current leakage of the FET. In another aspect, a body connection implant that is formed to short a source or drain region to a body of the FET is extended in length to form body connection implant regions underneath at least a portion of the edge gate regions. In this manner, the work functions of the edge gate regions are increased in voltage thus increasing the threshold voltage of the edge transistors and reducing current leakage of the edges transistors and the FET.

Abstract: An integrated device that includes a substrate, a circuit region located over the substrate, a design keep out region located over the substrate, and a periphery structure located over the substrate. The design keep out region laterally surrounds the circuit region. The periphery structure includes a first plurality of interconnects that laterally surrounds the design keep out region. The periphery structure is configured to operate as an electrical seal ring and a mechanical crack stop.

Abstract: This disclosure provides systems, methods and apparatus for capacitive touch sensing. In one aspect, a chip seal ring having an integrated capacitive sense plate is provided. In some implementations, a capacitance of the integrated sense plate to a finger may be used to detect the presence of the finger. In some implementations, a fringe capacitance of the seal ring sense plate to the finger is used to detect the presence of the finger. The chip may be sensor chip, for example, a fingerprint sensor chip, and may be implemented in an electronic device.

Abstract: A semiconductor die includes at least one process monitoring circuit for evaluating at least one process parameter of the semiconductor die. The at least one process monitoring circuit can include a first group of process monitoring circuits for monitoring NFET speed and a second group of process monitoring circuits for monitoring PFET speed. The process monitoring circuits can be distributed at the corners of the semiconductor die. The semiconductor die further includes a voltage control circuit configured to store optimum voltage information corresponding to the at least one process parameter. The voltage control circuit is further configured to selectively provide the optimum voltage information to a system power supply. The voltage control circuit includes a calculated optimum voltage register that stores the optimum voltage information corresponding to the at least one process parameter.

Abstract: One embodiment discloses receiving a number of parameter values for a multi-component circuit. From the received parameter values, a number of parasitic values for various components in the multi-component circuit are determined. For example, parasitic resistor values and parasitic capacitor values for transistors in the multi-component circuit are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the multi-component circuit. According to a disclosed embodiment, a layout of the multi-component circuit is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the multi-component circuit. As such, the parasitic values of the multi-component circuit have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the multi-component circuit for further circuit simulations.

Abstract: In one disclosed embodiment, a number of parameter values for an RF MOSFET are received. Examples of parameter values are style, bulk contact, finger width, finger length, number of fingers, current, and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. An RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation.

Abstract: In one embodiment, a number of parameter values for an inductor, such as a spiral inductor, are received. Examples of the parameter values are Number of Turns, Spacing, Width, Xsize, and Ysize parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the inductor are determined. For example, parasitic resistor values and parasitic capacitor values of the inductor are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the inductor. An inductor layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the inductor. As such, the parasitic values of the inductor have already been taken into account in the initial circuit simulation and, there is no need to extract the internal parasitics of the inductor for further circuit simulations.

Abstract: A diode for improved electrostatic discharge (ESD) protection against current failure includes a plurality of elongate anode and cathode conductor stripes each having first and second end portions of different widths to reduce current densities at feeder bus tie points, thereby reducing the possibility of current failure.

Abstract: In one disclosed embodiment, a number of parameter values for an RF MOSFET are received. Examples of parameter values are style, bulk contact, finger width, finger length, number of fingers, current, and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. An RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation.

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

Abstract: A transistor and a method of making a transistor are disclosed, where a tunnel diode is formed to make connection between the source of the transistor and the body node underlying the gate. For the example of an n-channel transistor, a p+ region is formed by implant and diffusion under the n+ source region, the p+ region in contact on one end with the relatively lightly doped p-type body node. The relatively high dopant concentration of both the p+ region and the n+ source region creates a tunnel diode. The tunnel diode conducts with very low forward voltages, which causes the body node region to be substantially biased to the potential of the source region. Methods for forming the transistor are also disclosed, including the use of a source/drain anneal prior to p-type implant, or alternatively a second sidewall oxide filament, to preclude the boron from counterdoping the LDD extension at the source side. Both silicon-on-insulator and bulk embodiments are disclosed.

Abstract: A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).

Abstract: An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.

Abstract: A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).

Abstract: An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.

Abstract: A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).