Abstract: Disclosed is a wire harness checker and a wire harness checking method, which are capable of determining whether a terminal of a terminal-fitted wire is adequately inserted in a connector housing, without contact with the wire and the terminal, objectively and reliably. Each of three pairs of sensor plates (20a, 20b; 30a, 30b; 40a, 40b) are disposed adjacent to an outer wall surface of a connector housing 10 in opposed relation to one another. An AC inspection signal is supplied to a terminal to be inserted into the connector housing 10, and detected from the terminal by each of the pairs of sensor plates (20a, 20b), (30a, 30b), (40a, 40b), to detect an insertion position of the terminal in the connector, in accordance with a relative value of each detection signal from the sensor plates, so as to determine adequacy of the insertion position.

Abstract: Disclosed is a conductor inspection apparatus capable of detecting a state of an inspection-target electric conductor with a high degree of accuracy in a non-contact manner. The inspection apparatus includes a signal supply section 510 for supplying an inspection signal to an inspection-target conductor 520, and two sensor plates 570, 580 disposed approximately parallel to each other in the vicinity of the conductor 520. The inspection apparatus is designed to inspect a configuration of the conductor 520 disposed opposed to the sensor plate 570, in accordance with a measured signal level from the sensor plate 570.

Abstract: Disclosed is a wire harness checker and a wire harness checking method, which are capable of determining whether a terminal of a terminal-fitted wire is adequately inserted in a connector housing, without contact with the wire and the terminal, objectively and reliably. Each of three pairs of sensor plates (20a, 20b; 30a, 30b; 40a, 40b) are disposed adjacent to an outer wall surface of a connector housing 10 in opposed relation to one another. An AC inspection signal is supplied to a terminal to be inserted into the connector housing 10, and detected from the terminal by each of the pairs of sensor plates (20a, 20b), (30a, 30b), (40a, 40b), to detect an insertion position of the terminal in the connector, in accordance with a relative value of each detection signal from the sensor plates, so as to determine adequacy of the insertion position.

Abstract: Disclosed is a conductor position inspection apparatus capable of detecting where an inspection-target electric conductor is located, with a high degree of accuracy in a non-contact manner. The inspection apparatus comprises a signal supply section 510 for supplying an AC inspection signal to an inspection-target conductor 520, two sensor plates 570, 580 disposed approximately parallel to each other in the vicinity of the conductor 520, a subtracter 550 for subjecting respective detected signal values from the sensor plates to subtraction, and a divider 560 for dividing the detected signal value from a selected one of the sensor plates by the subtraction result to normalize the detected signal value from the selected sensor plate so as to detect a relative ratio between the detected signal values from the sensor plates to obtain a value X corresponding a distance between the selected sensor plate and the conductor 520, as a detection result.

Abstract: Disclosed is a conductor inspection apparatus capable of capable of detecting a state of an inspection-target electric conductor with a high degree of accuracy in a non-contact manner. The inspection apparatus comprises a signal supply section 510 for supplying an inspection signal to an inspection-target conductor 520, and two sensor plates 570, 580 disposed approximately parallel to each other in the vicinity of the conductor 520. The inspection apparatus is designed to inspect a configuration of the conductor 520 disposed opposed to the sensor plate 570, in accordance with a measured signal level from the sensor plate 570.

Abstract: A time measuring device includes: an input signal detecting unit for detecting three or more edges in an input signal and to output three or more detection signals in parallel, the three or more detection signals changing based on the three or more edges, respectively; a converting unit for converting phase differences between change timings of the detection signals and clock edges in a reference clock having a predetermined operating frequency into analog voltage values, respectively; a counting unit for counting, from change timings of at least two of the detection signals, number of the clock edges between the clock edges from which at least two detection signals are respectively delayed by the phase differences corresponding to at least two detection signals; an operating unit for calculating a time interval between edges of the three or more edges based on the analog voltage values and the number of clock edges.

Abstract: A time measuring device includes: an input signal detecting unit for detecting three or more edges in an input signal and to output three or more detection signals in parallel, the three or more detection signals changing based on the three or more edges, respectively; a converting unit for converting phase differences between change timings of the detection signals and clock edges in a reference clock having a predetermined operating frequency into analog voltage values, respectively; a counting unit for counting, from change timings of at least two of the detection signals, number of the clock edges between the clock edges from which at least two detection signals are respectively delayed by the phase differences corresponding to at least two detection signals; an operating unit for calculating a time interval between edges of the three or more edges based on the analog voltage values and the number of clock edges.

Abstract: A diagnostic apparatus for detecting failure points in an electronic circuit through a non-contact fashion. The diagnostic apparatus includes means for applying a diagnostic support program to activate components in the electronic circuit under test, a detector array for detecting voltage signals representing electric fields of various locations in the electronic circuit under test, a measurement unit for converting the voltage signals to measured data representing negative peak rates Mpr, a processing unit for determining defective points in the electronic circuit under test based on measured data representing the negative peak rates Mpr and supplemental information in data bases produced in advance, and a display for displaying the defective points specified by the processing unit.

Abstract: A fractional time frequency measuring apparatus includes a divider for dividing a frequency of a signal to be measured with a predetermined division factor; a counter unit for counting the divided signal with a standard clock for every period of the divided signal and outputting count results; a fractional time measuring unit for measuring fractional times produced by the counting with the standard clock; a sequence control unit to form a sequence circuit for sequentially counting the divided signal with the standard clock; a memory unit for holding the count results from the counter unit; a microprocessor for determining a value of the divisional factor, generating a reset signal, and calculating the frequency of the signal to be measured from the count results stored in the memory unit.

Abstract: An analog arithmetic circuit directly divides an input voltage by another input voltage with high accuracy without requiring a logarithmic conversion process or an adjustment process. The analog arithmetic circuit includes: an integrator for integrating a dividend signal and a feedback signal; a hysteresis comparator having two threshold levels to compare an output signal of the integrator and generates a comparison output; a limiter which receives the comparison output and a divisor signal and generates the feedback signal that is proportional to the divisor signal; an average circuit connected to an output of the hysteresis comparator to generates an average value of the comparison output as a quotient signal.

Abstract: A pulse measuring instrument for measuring various pulse signal parameters such as the pulse width, the signal period of an input signal, and the time interval between input signals is capable of measuring the signal parameters with a high degree of accuracy and simplicity by automatically calibrating the propagation time difference between the input signal paths in the circuit configuration in the measuring instrument. The pulse signal measuring instrument is first provided with a calibration signal at the input terminal to obtain calibration data. The calibration data includes various time difference data regarding signal propagation time difference between the different signal paths in the measuring instrument. The calibration data also includes the signal period of the calibration signal and standard pulse width of the calibration signal. The calibration data is stored in a computer in the pulse signal measuring instrument.

Abstract: Based on a desired center frequency and a frequency resolution for a signal to be measured which are entered via an operator section, a micro-CPU calculates the frequency dividing number, a preset value and a center value for the signal to be measured. The frequency dividing number is set in a frequency divider, which frequency divides the signal to be measured and provides the frequency-divided output to a continuous period-to-voltage converter. The continuous period-to-voltage converter counts clock pulses occurring in each frequency-divided period, measures the difference between fractions of time from both the beginning and the end of the frequency-divided period to the generation of the next clock pulses, respectively, and outputs, as a voltage corresponding to the frequency-divided period, the sum of a voltage corresponding to a predetermined number of consecutive low-order bits of a binary value, obtained by adding the preset value to the pulse count value, and the fractional time difference.

Abstract: A time interval measuring apparatus for measuring a time interval between two input signals and a signal period of either one of the input signals is capable of detecting and canceling the time difference in the signal propagation times between the two signal paths which transmit two input signals to be measured to an inner circuit of the time interval measuring apparatus. The true time interval is calculated by using the first time interval measurement result obtained when the first and second switches are switched to the first and second input terminals respectively, and the second time interval measurement result obtained when the second and first switches are switched to the first and second input terminals respectively, and the signal period of the input signal. The difference between the signal propagation times in the two input signal paths is canceled by the calculation part. The true time interval, the signal period and the phase difference between the input signals are displayed on the display.

Abstract: Periods P.sub.k between the one edges of input pulses are measured one after another by a successive period measuring circuit, and at the same time, the time interval between the one edge to the other of each input pulse, that is, a pulse width W.sub.k, is measured by a time interval measuring circuit. The measured periods are sequentially accumulated and each accumulated value is made to correspond to each pulse, as the time at which the measurement of its pulse width was started. In an interpolation part, pulse widths, which are assumed to be obtained at regular time intervals, are computed, by an interpolation method, from the sequence of measured pulse widths and the their measurement starting times. In a Fourier transform part, the pulse width data obtained by the interpolation is subjected to a Fourier transform to obtain the frequency components of a pulse width jitter.

Abstract: In a high-speed data multiplexing device with a plurality of data multiplexing circuits there are included in each data multiplexing circuit a frequency divider for frequency dividing the same clock and a logic circuit for time division multiplexing input data of a plurality of channels in accordance with the output of the frequency divider. The outputs of the frequency dividers are subjected to a logical operation by a gate circuit. A voltage corresponding to the duty ratio of the operated output from the gate circuit is compared with a reference voltage in a detector/controller section. It is determined, based on the result of comparison, whether or not the frequency dividing phases of the frequency dividers of the data multiplexing circuits are uniform, and if not, a reset signal is applied to the frequency dividers to reset them to thereby make their frequency dividing phases uniform.

Abstract: An input pattern is re-timed in a re-timing circuit by an input clock signal of the same frequency as that of the input pattern, and the re-timed input pattern and a reference pattern generated by a reference pattern generator in synchronization with the input clock signal are compared by a digital error detector to detect a mismatch between them. When the error rate dependent on the thus detected mismatch is larger than a predetermined value, an inhibit control circuit inhibits one input clock pulse which is applied to the reference pattern generator, and when the error rate is smaller than the predetermined value, the inhibit control circuit generates a pattern synchronization establishment signal. When the pattern synchronization establishment signal disappears, a one-shot circuit generates a pulse of a certain width, and if the pattern synchronization establishment signal is not generated again in this while, a T flip-flop is triggered by the trailing edge of the pulse of the certain width.

Abstract: Frequency division circuits in n stages sequentially 1/2-frequency-divide an input clock signal. Pattern generating circuit generates and issues a plurality of pattern data parallel to each other in synchronism with a frequency-divided clock from the final frequency division stage thereof. Multiplexing circuits in n stages are given a plurality of pattern data and multiplex input pattern data in each stage for each two data. Output clock signals of the n-th through first stage frequency division circuits are supplied to the first through n-th multiplexing circuits via respective delay circuits as multiplexing control clock signals. A retiming circuit is inserted in series to the input of at least one of the multiplexing circuits, and a multiplexing control clock signal applied to said one multiplexing circuit from the corresponding frequency division circuit is given to the retiming circuit as a retiming clock signal.

Abstract: A pseudo random pattern generating device generates a pseudo random pattern, which recurs on a cycle of (2.sup.n -1) bits. The device sequentially converts from parallel to serial form 2.sup.m -bit patterns read out of a pattern memory having stored at each address a subpattern composed of one of 2.sup.n-m split patterns. A basic pseudo random pattern is split at intervals of 2.sup.m bits and a continuation pattern of a predetermined number of bits subsequent to each split pattern in the recurring random pattern. A pattern of 2.sup.m bits to be taken out of each subpattern which is read out of the pattern memory is shifted one bit position upon each readout of 2.sup.n-m subpatterns.

Abstract: A clock regenerator generates a clock Co synchronized with an input data pattern and a data pattern generator generates a reference data pattern in synchronization with the clock Co. The reference data pattern and the input data pattern are compared by a data disagreement detector to detect disagreement therebetween. The disagreement detection signal thus obtained is frequency divided by a 1/m-frequency divider and its frequency-divided output is further frequency divided by a 1/-n frequency divider. The frequency-divided output of the 1/n-frequency divider is provided to a bistable flip-flop, placing it in one stable state. The logical sum of the output of the flip-flop in the one stable state and the 1/m-frequency divider is obtained, as an inhibit pulse, by an AND gate, and the inhibit pulse is applied to another AND gate to inhibit the passage therethrough of the clock Co to the data pattern generator, delaying the generation of the reference data pattern in the data pattern generator.

Abstract: Sampling pulses for determining a series of measurement periods are each synchronized, by a synchronizing circuit, with one of a plurality of input signal pulses to be measured. A first counter responds to the synchronized sampling pulse to start the counting of the input signal pulses. When the first counter has counted a predetermined number M of input signal pulses, a second counter starts counting the input signal pulses at the initial value M and stops the counting in response to the next synchronized sampling pulse. The count value of the second counter is applied to a display during the next counting of the input signal pulses by the first counter up to the predetermined number.