Abstract: A new distributed control mechanism for managing bi-directional interfaces of symmetrical multiprocessor systems in such a manner as to minimize the latency to storage, yet fairly distribute the use of the interfaces amongst the various components. This bi-directional interface can be designed to perform with differing characteristics depending upon the direction of information flow. These characteristics are implemented into the control logic of the source and destination components interconnected by the bi-directional interface, thus yielding two interface behaviors using only one interface. Each component is able to track the state of the interface by using only its own request state in conjunction with the detected request state of the opposing component, when both units are operating under the joint control algorithm present in the control logic of the source and destination component.

Abstract: A control system and interface is provided for controlling the transmission of address and data signals via independently operative bi-directional address and data interfaces, respectively, within a data processing system. The system allows address signals to be transferred via the address interface either before, or after, associated data signals are transferred. The address interface operates at a rate which is independent of the rate achieved on the data interface. Address signals transferred on the address interface are stored in one of a plurality of address storage devices depending on request type. A routing circuit associates later-provided data signals with the address storage device storing the associated address signals, and a correlation circuit allows the address storage device to record the data transfer with the associated address signals. According to one embodiment, the correlation is performed using a pointer indicative of a storage location temporarily storing the data signals.

Abstract: A serial speed-matching buffer for transferring data signals between a selectable one of multiple transferring units to one or more receiving units. The serial speed-matching buffer has a plurality of registers which may each be selectably configured in load mode to receive data signals from selectable ones of the transferring units. Data signals provided to the speed-matching buffer from a selectable one of the transferring units may be made available to the receiving unit during the next clock period. This is an improvement over a rank-of-registers speed-matching buffer which generally inflicts a delay prior to the first word of any transfer. When not conditioned in load mode, each of the registers defaults to a serial chain mode in which data signals may be received from an associated adjacent one of the registers, and wherein a predetermined one of the registers provides data signals at the receiving rate.

Abstract: An improved conflict detection system for use in maintaining memory coherency in a multiprocessor, shared-cache memory system. The system includes a queue for storing pointers to request addresses that resulted in cache misses. The addresses associated with the queued pointers will generally be presented to a main memory for processing based on a predetermined priority scheme. The system further includes conflict detection logic which uses the queue pointers and the request addresses provided by associated ones of the processors to determine if any two of the queued requests are associated with the same request address. If so, a conflict exists, and the request queue later in time must be re-directed to cache instead of being presented to main memory to maintain cache coherency. The system further includes a mechanism for using pointers to detect conflict situations associated with flush and replacement cache operations.

Abstract: A system and method for monitoring and collecting performance characteristics of a target system and providing the results by way of time-division multiplexing is provided. The performance monitor includes a mechanism for latching a plurality of performance attribute signals. An output circuit, coupled to the latching mechanism, is used to output the latched performance attribute signals in groups, wherein each of the groups is a subset of all of the performance attribute signals. The performance monitor further includes a time division circuit coupled to the output circuit, to allow the output circuit to output each of the groups of performance attribute signals at different times. Each group of performance attribute signals can therefore be transmitted via common output access points, although at different times as the groups are transmitted in succession.

Abstract: A multiprocessor data processing system having store-through first-level caches with separate instruction and operand sections and a store-in second-level cache that is shared between the processors and which has separate instruction and operand sections. Dual second-level caches, each mappable to all of shared memory, enhance cache performance. The second-level cache memory space is divided into a plurality of segments, with each segment having a dedicated instruction tag memory, a dedicated operand tag memory, a dedicated instruction cache memory, and a dedicated operand cache memory. The segments may be addressed in parallel to further enhance cache performance.