Abstract: A non-volatile memory module includes a charging circuit, a battery couple to the charging circuit, a volatile memory and an electronic switch coupled between the volatile memory and the battery.

Abstract: A data storage system includes a multi-tasking processor which manages a write cache to identify adjacent blocks held in the write cache which are to be included in a next write operation, while at the same time handling data transfer requests from a system host. The processor monitors the write cache and when the cache has fewer than a predetermined number of storage locations free, initiates a block-merge task. The processor then determines which block in the write cache is least recently used and, based on virtual block numbers assigned to the data blocks, identifies the blocks in the write cache which are adjacent to the least recently used block and are within the same chunk as that block. The processor maintains a list of these adjacent blocks and the locations in which the blocks are held in the write cache.

Abstract: A page mode/nibble mode dynamic random access memory (DRAM) comprising row and column decoders, the column decoder further comprising a column address buffer and a column address buffer counter. The page mode/nibble mode DRAM also comprises a buffer controller means adapted to receive a write enable signal and to determine whether the DRAM should be placed in a page mode or a nibble mode to facilitate the particular memory access requested by a memory controller. An asserted write enable signal, may indicate, for example, a write operation, thereby calling for the page mode/nibble mode DRAM to move into a page mode to effectuate the write operation. The page mode/nibble mode DRAM also utilizes the write enable signal in the conventional manner, to indicate the initiation of a particular type of memory access, namely a write operation or a read operation.

Abstract: An error injection test scripting system that permits a test engineer to select from a series of commands those that will induce a desired test scenario. These commands are presented to a parser, either in command line form or as a batch of commands, which parses the syntax of the commands and associated parameters, to create a task list which is communicated to a scheduler. The scheduler handles the execution of the tasks in the list, converts parameters to explicit logical block test sequences and maintains test results. Tasks such as error injection use a special protocol (which the unit under test must be able to understand and interpret) to circumvent standard bus and controller protocols, so that test data, such as corrupt parity or multiple hard error failures can be sent to the disks in the RAID system, while bypassing the RAID array management functions that would otherwise automatically correct or prevent the errors.

Abstract: A data storage system includes a multi-tasking processor which manages a write cache to identify adjacent blocks held in the write cache which are to be included in a next write operation, while at the same time handling data transfer requests from a system host. The processor monitors the write cache and when the cache has fewer than a predetermined number of storage locations free, initiates a block-merge task. The processor then determines which block in the write cache is least recently used and, based on virtual block numbers assigned to the data blocks, identifies the blocks in the write cache which are adjacent to the least recently used block and are within the same chunk as that block. The processor maintains a list of these adjacent blocks and the locations in which the blocks are held in the write cache.

Abstract: Read-write buffer apparatus is provided for reducing the time necessary to resolve read conflicts during normal and block mode read requests. Additionally, the read-write buffer apparatus provides a means for gathering non-sequential write requests in an internal write buffer, thus reducing the frequency of a buffer full condition. The enhanced read-write buffer apparatus minimizes CPU wait states, while increasing the CPU processing rate and improves overall data processing system throughput.

Abstract: A method for reducing the number of I/O requests required to write data to a disk drive of a computer system. The computer system includes a read cache for storing old data read from the disk drive, and a write cache for storing new data to be written to the disk drive. The method selectively merges old data in the read cache with new data in the write cache to form at most two physically contiguous data segments which can be written to the disk drive with at most two I/O requests.

Abstract: A system for reducing the number of I/O requests required to write data to an redundant array of inexpensive disks (RAID) of a computer system including a host central processor unit and a memory buffer cache. The system includes determinations for writing new data stored in the cache to the disk drives, as stripes, using the least number of I/O requests possible. The system uses the best of two alternative techniques in which the parity for the stripe can be generated. A first procedure determines the number of I/O requests that would be required to generate the parity data from the entire stripe including the new data to be written to the disk drives. A second procedure determines the number of I/O requests that would be required to generate the parity data from the new data to be written to the disk drives and the old parity data of the stripe.

Abstract: A method for prefetching the data and parity blocks for generating parity data of a stripe. The method uses a low and high thresholds marker indicative of a first and second level of fullness of the cache to determine whether or not to prefetch the data and parity blocks. If the cache is filled to a level exceeding the first level of fullness, the data and parity blocks are prefetched for any blocks to be written to the disk drive between the low and high threshold. The data and parity blocks are read from the disk drive at a lower processing priority in anticipation of the writing of the block.

Abstract: Read-write buffer apparatus is provided for reducing the time necessary to resolve read conflicts during normal and block mode read requests. Additionally, the read-write buffer apparatus provides a means for gathering non-sequential write requests in an internal write buffer, thus reducing the frequency of a buffer full condition. The enhanced read-write buffer apparatus minimizes CPU wait states, while increasing the CPU processing rate and improves overall data processing system throughput.

Abstract: Apparatus for processing a stream of bits including a hardware comparator that compares first predetermined bits of the stream, comparison input means to provide a table of comparison values to said hardware comparator for comparison with said predetermined bits of said stream, the comparison input means being programmmable to provide one of a plurality of different tables in response to a table select control signal, an index generator for generating an index based on the states of the predetermined bits, and a processor for accessing the index and processing a group of the bits in at least one of a plurality of different ways based on the index.