Abstract: Devices systems and methods are disclosed providing a highly fault tolerant Command, Control, and Data Handling (CC&DH) system immune to byzantine faults. The system includes a plurality of High Integrity Computing Elements each capable of delivering data immune to byzantine faults, an arbitrary communication interface, and a number of peripheral devices providing input and output to the system. The system is capable of providing high integrity data immune to byzantine faults throughout the system. Using one greater High Integrity Computing Elements than the number of faults required allows for implementation of a wide range of redundant systems including dual, triple, quad, and beyond redundancy using voting computers. The system is implemented using any number of standard computing elements, which is greater than two, a communication abstraction, data exchange, mission algorithm, and data comparison producing data immune to byzantine errors to the remaining peripherals in the system.

Abstract: A robotic system includes a plurality of robotic elements, each having at least one processing component, at least one memory component, and an I/O interface; and a virtual backplane coupling the plurality of robotic elements.

Abstract: A communication network comprises a communication bus and at least two line cards. Each of the line cards are coupled to the communication bus The line cards comprise a processor and a configuration memory coupled to the processor. The communication occurring on the communication bus is predetermined, but can be reconfigured during real time operation by events or by the addition or subtraction of line cards. The configuration memory comprising an array of configuration tables, each configuration table storing a listing of processes to run and data to be transmitted or received by the process. A current configuration table is selected from the array of configuration tables upon the occurrence of a predefined event.

Abstract: A robotic system includes a plurality of robotic elements, each having at least one processing component, at least one memory component, and an I/O interface; and a virtual backplane coupling the plurality of robotic elements.

Abstract: Method and apparatus are provided for preventing faulty commercial-off-the-shelf (COTS) peripherals or I/Os from disabling the bus to which they are connected. The apparatus has isolators coupled to the bus and the I/Os. A controller is coupled between the interfaces, a processor and memory, operating such that an I/O cannot transfer data to the bus without permission from the bus. Isolation memory keeps I/O and bus messages separate. I/O messages are checked before being sent to the bus. The method comprises: determining if there is a message for the peripheral, temporarily storing the message, determining if the message is for output or input, and if for output, sending it to the peripheral, and if for input, requesting and receiving it from the peripheral, temporarily storing and checking it, and transferring it to the bus only if valid. This prevents a failed I/O or peripheral from disabling the bus.

Abstract: A digital motor controller circuit including a an energy storage device, a bus protection circuit, an input signal selector, a combiner, a calibration device for altering parameters for different applications, a compensator, a motor driver circuit, and feedback circuitry for controlling a motor with a minimum of cost and space requirements.

Abstract: A digital motor controller circuit including a an energy storage device, a bus protection circuit, an input signal selector, a combiner, a calibration device for altering parameters for different applications, a compensator, a motor driver circuit, and feedback circuitry for controlling a motor with a minimum of cost and space requirements.

Abstract: A motor controller circuit including an energy storage device, a bus protection circuit, an input signal selector, a combiner, a compensator, a modulator, a motor driver circuit, a commutator, a feedback circuitry and a plurality of filters, resistors, inductances, capacitances and optical isolators all contained on a single circuit board for use in controlling a motor with a minimum of cost and space requirements.

Abstract: A task scheduler system including an array of priority queues for use in a real time multitasking operating system including equation lists, configuration lists, a function library, input and output drivers, user-created task definition lists of major and minor tasks and interrupt handlers. The system includes task scheduling apparatus which, upon the completion of each library function, interrogates the priority queues and finds the highest priority task segment whose requested resource is available and executed, and which executes task segments in the same priority queue in round-robin fashion. The system further includes task creation apparatus and apparatus for maintaining the status of all major tasks in a system in the states of unlocked and done, unlocked and active, unlocked and waiting, locked and active, or locked and waiting.