Abstract: Methods and systems for circuit design are described. A tool may detect a timing violation on a signal path connected to a local clock buffer in a circuit model. The local clock buffer may be configured to generate a first clock signal having a first pulse width. The tool may determine a first metric associated with a first type of timing violation, and may determine a second metric associated with a second type of timing violation different from the first type of timing violation. The detected timing violation may be one of the first type and second type of timing violations. The tool may, based on the first metric and the second metric, determine whether to retain the generation of the first clock signal or to configure the local clock buffer to generate a second clock signal having a second pulse width different from the first pulse width.

Abstract: Methods and systems for circuit design are described. A tool may detect a timing violation on a signal path connected to a local clock buffer in a circuit model. The local clock buffer may be configured to generate a first clock signal having a first pulse width. The tool may determine a first metric associated with a first type of timing violation, and may determine a second metric associated with a second type of timing violation different from the first type of timing violation. The detected timing violation may be one of the first type and second type of timing violations. The tool may, based on the first metric and the second metric, determine whether to retain the generation of the first clock signal or to configure the local clock buffer to generate a second clock signal having a second pulse width different from the first pulse width.

Abstract: A computer implemented method for correcting early mode slack fails in an electronic circuit can include generating a logical description of an electronic circuit having a path from first circuit to a second circuit. The method then include compiling the logical description into a technology specific representation of the circuit. The method may further include determining that the path has an early mode slack fail. The method may be continued by identifying, in response to determining that a second path has a first early mode slack fail, a complex logic gate located in the second path and having an output coupled to the input of the second circuit that can be decomposed into two or more logic gates. The method may then conclude by decomposing, by processor, the complex logic gate into a two or more logic gates to address the early mode slack fail.

Abstract: A computer implemented method for correcting early mode slack fails in an electronic circuit can include generating a logical description of an electronic circuit having a path from first circuit to a second circuit. The method then include compiling the logical description into a technology specific representation of the circuit. The method may further include determining that the path has an early mode slack fail. The method may be continued by identifying, in response to determining that a second path has a first early mode slack fail, a complex logic gate located in the second path and having an output coupled to the input of the second circuit that can be decomposed into two or more logic gates. The method may then conclude by decomposing, by processor, the complex logic gate into a two or more logic gates to address the early mode slack fail.