Abstract: A semiconductor device includes a semiconductor substrate, a heat generating device, and a heat radiating part. The heat generating device is provided on the semiconductor substrate, and the heat radiating part is provided above the heat generating device. The heat radiating part is thermally coupled with the semiconductor substrate through at least one contact part.

Abstract: A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.

Abstract: A design support program executed by a computer includes operations of: locating at least one via hole for coupling target wiring in a first layer in circuit information to wiring in a second layer being different form the first layer; calculating an area of the target wiring based on a length and a width of the target wiring; setting a division condition based on the area and a number of the via hole; dividing the target wiring into divided wirings at a position other than a position where the via hole is provided based on the division condition; generating connection information indicating a connection relationship between the divided wirings and limitation information for coupling the divided wirings via a wiring in a third layer being different from the first layer; and outputting the connection information, the limitation information and circuit information obtained after dividing.

Abstract: A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate, a heat generating device, and a heat radiating part. The heat generating device is provided on the semiconductor substrate, and the heat radiating part is provided above the heat generating device. The heat radiating part is thermally coupled with the semiconductor substrate through at least one contact part.

Abstract: A design support program executed by a computer includes operations of: locating at least one via hole for coupling target wiring in a first layer in circuit information to wiring in a second layer being different form the first layer; calculating an area of the target wiring based on a length and a width of the target wiring; setting a division condition based on the area and a number of the via hole; dividing the target wiring into divided wirings at a position other than a position where the via hole is provided based on the division condition; generating connection information indicating a connection relationship between the divided wirings and limitation information for coupling the divided wirings via a wiring in a third layer being different from the first layer; and outputting the connection information, the limitation information and circuit information obtained after dividing.

Abstract: A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.

Abstract: An input circuit writes an expected value to one end of an evaluation wiring. A latch circuit latches a logic level of the other end of the evaluation wiring. A first switch circuit connects an output of the input circuit to the input of the latch circuit. A second switch circuit connects the output of the input circuit to the one end of the evaluation wiring. A third switch circuit connects the other end of the evaluation wiring to the input of the latch circuit. By turning on, off, and off the first to third switch circuits, respectively, the output of the input circuit is directly connected to only the input of the latch circuit. In this state, the input circuit writes an expected value, and a logic level is read from the latch circuit. Accordingly, failure of the evaluation wiring can be easily discriminated from other failure.

Abstract: An input circuit writes an expected value to one end of an evaluation wiring. A latch circuit latches a logic level of the other end of the evaluation wiring. A first switch circuit connects an output of the input circuit to the input of the latch circuit. A second switch circuit connects the output of the input circuit to the one end of the evaluation wiring. A third switch circuit connects the other end of the evaluation wiring to the input of the latch circuit. By turning on, off, and off the first to third switch circuits, respectively, the output of the input circuit is directly connected to only the input of the latch circuit. In this state, the input circuit writes an expected value, and a logic level is read from the latch circuit. Accordingly, failure of the evaluation wiring can be easily discriminated from other failure.