Patents by Inventor Mitsuaki Kai

Mitsuaki Kai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6867106
    Abstract: The semiconductor device comprises: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: March 15, 2005
    Assignee: Fujitsu Limited
    Inventors: Seiichiro Yamaguchi, Mitsuaki Kai, Isao Amano
  • Patent number: 6753574
    Abstract: The semiconductor device includes: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: June 22, 2004
    Assignee: Fujitsu Limited
    Inventors: Seiichiro Yamaguchi, Mitsuaki Kai, Isao Amano
  • Publication number: 20030132464
    Abstract: The semiconductor device comprises: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 17, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Seiichiro Yamaguchi, Mitsuaki Kai, Isao Amano
  • Publication number: 20020048972
    Abstract: The semiconductor device comprises: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.
    Type: Application
    Filed: March 23, 2001
    Publication date: April 25, 2002
    Applicant: Fujitsu Limited
    Inventors: Seiichiro Yamaguchi, Mitsuaki Kai, Isao Amano