Patents by Inventor Mitsugu Tanaka

Mitsugu Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734300
    Abstract: A semiconductor device according to the present invention includes the following: a conductive layer disposed on an insulating substrate; a first semiconductor element and a second semiconductor element that are joined on an opposite surface of the conductive layer opposite from the insulating substrate, with a gap the first semiconductor element and the second semiconductor element; an electrode joined on an opposite surface of the first semiconductor element opposite from the conductive layer, and an opposite surface of the second semiconductor element opposite from the conductive layer, so as to extend over the gap; and resin sealing the conductive layer, the first semiconductor element, the second semiconductor element, and the electrode. The conductive layer has a recess pattern that is disposed on a surface being opposite from the insulating substrate and facing the gap, the recess pattern extending along the gap.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: August 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mitsugu Tanaka, Yusuke Ishiyama, Akitoshi Shirao
  • Publication number: 20190295915
    Abstract: A semiconductor device according to the present invention includes the following: a conductive layer disposed on an insulating substrate; a first semiconductor element and a second semiconductor element that are joined on an opposite surface of the conductive layer opposite from the insulating substrate, with a gap the first semiconductor element and the second semiconductor element; an electrode joined on an opposite surface of the first semiconductor element opposite from the conductive layer, and an opposite surface of the second semiconductor element opposite from the conductive layer, so as to extend over the gap; and resin sealing the conductive layer, the first semiconductor element, the second semiconductor element, and the electrode. The conductive layer has a recess pattern that is disposed on a surface being opposite from the insulating substrate and facing the gap, the recess pattern extending along the gap.
    Type: Application
    Filed: December 8, 2016
    Publication date: September 26, 2019
    Inventors: Mitsugu TANAKA, Yusuke ISHIYAMA, Akitoshi SHIRAO
  • Patent number: 8518751
    Abstract: A method of manufacturing a semiconductor device comprises: preparing a lead frame including a package external region and a package internal region, a burred surface being provided at a top end of a side of the lead frame, and a fracture surface being provided in the vicinity of the top end of the side; chamfering the top end of the side in the package external region; mounting a semiconductor element on the lead frame and sealing the semiconductor element with mold resin in the package internal region; and removing resin burr provided on the side of the lead frame in the package external region after the chamfering and the sealing.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: August 27, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ken Sakamoto, Taketoshi Shikano, Mitsugu Tanaka, Taishi Sasaki
  • Publication number: 20120196405
    Abstract: A method of manufacturing a semiconductor device comprises: preparing a lead frame including a package external region and a package internal region, a burred surface being provided at a top end of a side of the lead frame, and a fracture surface being provided in the vicinity of the top end of the side; chamfering the top end of the side in the package external region; mounting a semiconductor element on the lead frame and sealing the semiconductor element with mold resin in the package internal region; and removing resin burr provided on the side of the lead frame in the package external region after the chamfering and the sealing.
    Type: Application
    Filed: August 19, 2011
    Publication date: August 2, 2012
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ken Sakamoto, Taketoshi Shikano, Mitsugu Tanaka, Taishi Sasaki
  • Patent number: 6873820
    Abstract: In an image forming apparatus and an image forming method, a paper position aberration detecting sensor including a light emitting element and a light receiving element is disposed in the paper conveying path of the image forming apparatus. The amount of paper position aberration in paper conveyance is detected by a counter, and on the basis of the result of the detection, a CPU controls the writing start position of a printed image.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: March 29, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mitsugu Tanaka, Eiichiro Teshima, Takuya Mukaibara, Tadashi Okanishi
  • Patent number: 6594530
    Abstract: The present invention is a block oriented control system that allows interoperability between devices made by different manufacturers. A block oriented control system is a system which includes a plurality of field devices incorporating a physical layer, communication stack, and user layer, with the field devices being connected by a transmission medium, such as a bus. The physical layer receives signals from the bus and translates the signals into a message for the communications stack, and receives messages from the communications stack and translates the messages into signals for the bus. The communication stack controls the communications between devices operating in the control system. The user layer is a block oriented approach to the system's control functions, and includes function blocks and system management. The function blocks are standardized encapsulations of control functions, such as analog input or proportional/derivative.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: July 15, 2003
    Assignee: Fieldbus Foundation
    Inventors: David A. Glanzer, Terrence L. Blevins, Ram Ramachandran, Kenneth D. Krivoshein, Patricia E. Brett, Jack Elias, William R. Hodson, Frank Lynch, Ashok K. Gupta, Lee A. Neitzel, Thomas B. Kinney, Chuji Akiyama, Yasuo Kumeda, Hiroshi Mori, Mitsugu Tanaka
  • Publication number: 20030006492
    Abstract: A semiconductor device includes a resin sealing portion which has a plurality of side surfaces and a back surface which is formed between the side surfaces, a semiconductor chip which has a plurality of pads on a main surface thereof, a plurality of leads which are formed of conductor and each of which has a bonding portion, an external connection terminal portion and a cut portion, a plurality of wires which connect a plurality of leads and a plurality of pads of the semiconductor chip to each other, and a tab on which the semiconductor chip is mounted. By making the thickness of the cut portion of the lead smaller than the thickness of the external connection terminal portion, a lead sagging which is generated on the side surfaces of the resin sealing portion when the lead is cut by dicing after molding can be reduced.
    Type: Application
    Filed: May 31, 2002
    Publication date: January 9, 2003
    Inventors: Kazuto Ogasawara, Mitsugu Tanaka, Seiichi Tomihara
  • Publication number: 20020149805
    Abstract: This invention provides an image forming apparatus and an image forming method in which even if paper position aberration occurs, printed image position aberration is prevented from occurring by a simple methanism. A paper position aberration detecting sensor including a light emitting element and a light receiving element is disposed in the paper conveying path of the image forming apparatus, and the amount of paper position aberration in paper conveyance is detected by a counter, and on the basis of the result of the detection, a CPU controls the writing start position of a printed image.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 17, 2002
    Applicant: Canon Kabushiki Kaisha
    Inventors: Mitsugu Tanaka, Eiichiro Teshima, Takuya Mukaibara, Tadashi Okanishi
  • Patent number: 6424872
    Abstract: The present invention is a block oriented control system that allows interoperability between devices made by different manufacturers. A block oriented control system is a system which includes a plurality of field devices incorporating a physical layer, communication stack, and user layer, with the field devices being connected by a transmission medium, such as a bus. The physical layer receives signals from the bus and translates the signals into a message for the communications stack, and receives messages from the communications stack and translates the messages into signals for the bus. The communication stack controls the communications between devices operating in the control system. The user layer is a block oriented approach to the system's control functions, and includes function blocks and system management. The function blocks are standardized encapsulations of control functions, such as analog input or proportional/derivative.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: July 23, 2002
    Assignee: Fieldbus Foundation
    Inventors: David A. Glanzer, Terrance L. Blevins, Ram Ramachandran, Kenneth D. Krivoshein, Patricia E. Brett, Jack Elias, William R. Hodson, Frank Lynch, Ashok K. Gupta, Lee A. Neitzel, Thomas B. Kinney, Chuji Akiyama, Yasuo Kumeda, Hiroshi Mori, Mitsugu Tanaka
  • Patent number: 6084730
    Abstract: An information transmission system using data compression and/or error detection includes an information compression circuit for compressing digital information to generate compressed information. A record/reproducing device is provided for recording the compressed information on a recording medium, and reproducing the compressed information from the recording medium. Transmission circuitry is provided for transmitting the compressed information reproduced from the record/reproducing device to a transmission channel without expanding the compressed information. An information expansion circuit is then provided for expanding the compressed information which has been transmitted through the transmission channel in order to reproduce the digital information.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: July 4, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shingo Ikeda, Motokazu Kashida, Toshihiro Yagisawa, Masahide Hasegawa, Mitsugu Tanaka
  • Patent number: 5930453
    Abstract: In transferring image data between a first memory for storing image data in a first sequence and inputting and outputting the image data from and to a first data bus and a second memory for storing image data in a second sequence different from the first sequence and inputting and outputting the image data from and to a second data bus, the permission and the inhibition of the writing of the transferred image data to a transfer destination are controlled and the error detection/correction encoding/decoding is effected during the transfer to facilitate the address management and permit high speed processing of the image data.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: July 27, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuya Shimizu, Makoto Shimokoriyama, Mitsugu Tanaka, Katsumi Karasawa, Yoshiki Ishii, Yasuyuki Tanaka, Hidenori Hoshi
  • Patent number: 5764847
    Abstract: A digital signal recording apparatus is arranged to be capable of permitting long-time recording on one and the same recording medium without impairing the quality of audio signals at all. The apparatus has a first mode in which a digital video signal supplied from a video input circuit and having the amount of information not compressed by a video compression circuit is recorded on the recording medium by a recording circuit while all of n channel digital audio signals supplied from an audio input circuit are recorded by the recording circuit; and a second mode in which the digital video signal having the amount of information compressed by the video compression circuit and only part of the n channel digital audio signals supplied from the audio input circuit are recorded by the recording circuit.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: June 9, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsugu Tanaka
  • Patent number: 5751504
    Abstract: A digital signal recording apparatus is arranged to be capable of permitting long-time recording on one and the same recording medium without impairing the quality of audio signals at all. The apparatus has a first mode in which a digital video signal supplied from a video input circuit and having the amount of information not compressed by a video compression circuit is recorded on the recording medium by a recording circuit while all of n channel digital audio signals supplied from an audio input circuit are recorded by the recording circuit; and a second mode in which the digital video signal having the amount of information compressed by the video compression circuit and only part of the n channel digital audio signals supplied from the audio input circuit are recorded by the recording circuit.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: May 12, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsugu Tanaka
  • Patent number: 5740187
    Abstract: A data reproducing apparatus having: an error correcting circuit for correcting an error in an error correcting block in accordance with an error correcting code, the error correcting block including main information, at least one type of subsidiary information, an error detecting code at least for the main information, and the error correcting code for the main and subsidiary information and the error detection code; a flag memory circuit for storing an uncorrectable error flag to be set by the error correcting circuit for the at least one type of subsidiary information; a first interpolation circuit for interpolating the main information to correct an error in accordance with the decoding result by the error detecting code; and a second interpolation circuit for interpolating the at least one type of subsidiary information to correct an error in accordance with the uncorrected error flag stored in the flag memory circuit.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: April 14, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsugu Tanaka
  • Patent number: 5541739
    Abstract: A digital signal recording apparatus is arranged to be capable of permitting long-time recording on the same recording medium without impairing the quality of audio signals. The apparatus has a first mode in which a digital video signal supplied from a video input circuit and having the amount of information not compressed by a video compression circuit is recorded on the recording medium by a recording circuit while all of n channel digital audio signals supplied from an audio input circuit are recorded by the recording circuit; and a second mode in which the digital video signal having the amount of information compressed by the video compression circuit and only part of the n channel digital audio signals supplied from the audio input circuit are recorded by the recording circuit.
    Type: Grant
    Filed: October 10, 1995
    Date of Patent: July 30, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsugu Tanaka
  • Patent number: 5534929
    Abstract: A data processor in which input image data is coded by a coder, with the coded image data being stored in a memory. A controller controls a data amount of the coded image data which is output from the coder by comparing a predetermined set value and a data occupation ratio of the memory. The set value is changed in accordance with a transmission rate used when transmitting the coded image data. Audio data may be multiplexed with the output coded image data, with the timing of providing the audio data to the multiplexer being adjusted in accordance with the transmission rate.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: July 9, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsugu Tanaka
  • Patent number: 5507839
    Abstract: A dye is fixed to a solid material by using a diene or dienophile as the dye, incorporating a dienophile or diene into the solid material, effecting Diels-Alder reaction between the diene and the dienophile or between the dye and the solid material for binding the dye to the solid material. The dyed solid material has an increased dye concentration and prevents dye diffusion with the lapse of time.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: April 16, 1996
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Mitsugu Tanaka
  • Patent number: 5403811
    Abstract: A thermal transfer dye donating material comprising a support having thereon a dye donating layer which contains a thermo-mobile dye, wherein the thermo-mobile dye is a dye which can be represented by the general formula (I) indicated below.A--(L--B).sub.q (I)In this formula, A represents a dye residue which has an absorbance in the visible region and/or infrared region, L represents a divalent linking group or a simple bond, and B represents an atomic grouping which has the effect of suppressing the fading of the dye. Moreover, q is 1 or 2, and when q is 2, L and B may be the same or different.
    Type: Grant
    Filed: August 13, 1993
    Date of Patent: April 4, 1995
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Hisashi Mikoshiba, Mitsugu Tanaka, Masakazu Morigaki, Seiiti Kubodera
  • Patent number: 5345100
    Abstract: A semiconductor rectifier having a high breakdown voltage and a high speed operation is provided, which comprises a semiconductor substrate including a first semiconductor layer of one conductivity type and a second semiconductor layer of one conductivity type provided on the first semiconductor layer, a third semiconductor layer of an opposite conductivity type having a depth D and formed in the second semiconductor layer to provide a pn junction therebetween, the third semiconductor layer defining a plurality of exposed regions of the second semiconductor layer, each of the plurality of exposed regions of the second semiconductor layer having a width W, a relation between the depth D and the width W being given by D.gtoreq.0.5W, and a metal electrode provided on the substrate surface.
    Type: Grant
    Filed: September 13, 1993
    Date of Patent: September 6, 1994
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Takashi Kan, Masaru Wakatabe, Mitsugu Tanaka, Shinji Kunori, Akira Sugiyama
  • Patent number: 5326740
    Abstract: A thermal transfer image-receiving material having an image-receiving layer comprising a thermoplastic resin capable of receiving a dye, on a support, wherein the thermoplastic resin is a polyester having anti-fading groups in at least one of a main chain and a side chain moiety of the molecular structure of the thermoplastic resin and the material has the ability to form an image with a high image density and excellent image storage stability by thermal transfer recording.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: July 5, 1994
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Tetsu Kamosaki, Mitsugu Tanaka, Masakazu Yoneyama