Patents by Inventor Mitsuharu Nakazawa

Mitsuharu Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8482954
    Abstract: A semiconductor memory includes memory cells; word lines coupled to the memory cells; plate lines coupled to the memory cells; a selector that selects a first address signal in a first period and select a second address signal in a second period; a decode circuit that sequentially decodes the first and the second address signals selected by the selector, sequentially generates decode address signals based on the decoded first and second address signals, and sequentially activates the generated decode address signals; and a driver circuit that drives the word lines in accordance with the decode address signals activated based on the first address signal and drives the plate lines in accordance with the decode address signals activated based on the second address signal.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: July 9, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Mitsuharu Nakazawa
  • Publication number: 20110317507
    Abstract: A semiconductor memory includes memory cells; word lines coupled to the memory cells; plate lines coupled to the memory cells; a selector that selects a first address signal in a first period and select a second address ,signal in a second period; a decode circuit that sequentially decodes the first and the second address signals selected by the selector, sequentially generates decode address signals based on the decoded first and second address signals, and sequentially activates the generated decode address signals; and a driver circuit that drives the word lines in accordance with the decode address signals activated based on the first address signal and drives the plate lines in accordance with the decode address signals activated based on the second address signal.
    Type: Application
    Filed: September 1, 2011
    Publication date: December 29, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Mitsuharu NAKAZAWA
  • Patent number: 6392629
    Abstract: Disclosed is a liquid-crystal drive circuit having a simple configuration and being not susceptible to the characteristic of a device. The liquid-crystal drive circuit includes an auxiliary capacitor, applies a first voltage to a driving buffer, temporarily accumulates an output voltage of the driving buffer in the auxiliary capacitor, applies a voltage produced by subtracting the potential at the auxiliary capacitor from a second voltage to the driving buffer, and applies an output of the driving buffer onto a data bus.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: May 21, 2002
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Murakami, Mitsuharu Nakazawa, Ken-ichi Nakabayashi
  • Patent number: 6323918
    Abstract: A capacitor electrode is formed simultaneously with drain bus lines. This capacitor electrode is electrically connected to the contact of two TFT's through the medium of a contact hole. Then, an interlayer insulating film is formed on the entire face and a black matrix of such light blocking metal film as Ti is formed on the interlayer insulating film so as to overlie the channel parts and the contacts of the TFT's and the capacitor electrode. The capacitor electrode, the interlayer insulating film formed thereon, and the black matrix jointly form a capacitor.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: November 27, 2001
    Assignee: Fujitsu Limited
    Inventors: Koji Yoshioka, Masafumi Itokazu, Keizo Morita, Munehiro Haraguchi, Mitsuharu Nakazawa, Hiroshi Murakami
  • Patent number: 6243066
    Abstract: Disclosed is a liquid-crystal drive circuit having a simple configuration and being not susceptible to the characteristic of a device. The liquid-crystal drive circuit includes an auxiliary capacitor, applies a first voltage to a driving buffer, temporarily accumulates an output voltage of the driving buffer in the auxiliary capacitor, applies a voltage produced by subtracting the potential at the auxiliary capacitor from a second voltage to the driving buffer, and applies an output of the driving buffer onto a data bus.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: June 5, 2001
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Murakami, Mitsuharu Nakazawa, Ken-ichi Nakabayashi