Abstract: An encoding apparatus uses a vector quantization encoding method for encoding indexes of codewords, which supply a scalar quantized code of a maximum scalar product value of each code word in a code book, and its maximum scalar product value to a vector component of an input image inputted from an image sensor, so as to output the encoded indexes. A scalar product value calculating circuit in the encoding apparatus has scalar product value calculating sections, which are composed of an analog circuit having a code component capacitor corresponding to each code component, a differential amplifier and a feedback capacitor, corresponding to each codeword, and the scalar product values of the input vectors are calculated in parallel by the scalar product value calculating sections. In such a manner, when the analog calculation is made, the scale of the circuit can be decreased and the power consumption can be lowered.

Abstract: An image compressing apparatus employs a mean-separated normalized vector quantization method according to which, with respect to vector components corresponding to input images inputted from image sensors via a plurality of lines, encodes and outputs a scalar-quantized code of a mean value, a scalar-quantized code of a maximum scalar product value with each code word in a code book, and an index of one of the code words which yields a maximum scalar product value. In this image compressing apparatus, when the maximum scalar product value is less than a predetermined threshold value, in accordance with judgement by a comparator circuit, an output selecting circuit stops outputting the codes of the maximum scalar product value and of the index, and outputs only the code of the mean value. Therefore, when the image is uniform with pixels varying little in their luminance levels in compression processing unit blocks, code data to be outputted are restricted so that only data of the mean value are outputted.

Abstract: In respective comparators, a plurality of input voltages are compared with a comparison voltage that has been swept, and only the binary output of a D flipflop corresponding to the comparator that has exceeded the comparison voltage earliest is allowed to have "1", while the outputs corresponding to the rest of the comparators have "0". Therefore, it is possible to detect a maximum output by using the comparators of a normal CMOS construction and a binary-change detection means circuit constituted by logical circuits. Compared with the application of floating-gate MOS, this arrangement makes it possible to reduce costs, and also to easily carry out offset-voltage compensation for each comparator by using switched capacitors. As a result, in a maximum input detector which detects a maximum input from analog inputs through multiple channels by carrying out analog operations, it is possible to reduce costs, and also to improve detection precision.

Abstract: An inner product calculation device for calculating an inner product of a coefficient vector including at least one first element with a positive sign and at least one second element with a negative sign and an input vector including elements corresponding to a plurality of input voltages.

Abstract: A winner-take-all circuit for judging a channel receiving an analog signal having the largest or smallest value among multiple channels upon input of analog signals. Each basic circuit includes a detecting unit for comparing an input voltage with a reference voltage, and a feedback current generating unit for outputting a feedback current that determines a judging range in response to an output voltage from the detecting unit. The winner-take-all circuit also includes a tenth transistor serving as a common transistor to all the basic circuits. The tenth transistor secures, even when an input voltage is small, a current that should flow through a sixth transistor serially connected to the seventh transistor that determines an amount of a feedback current from the feedback current generating circuit.