Abstract: An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal (CK) and receives a data signal (DQ) and a strobe signal (DQS) from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal (DQS). The delay circuit includes a first adjustment circuit and a second adjustment circuit connected in series with the first adjustment circuit. The first adjustment circuit is capable of adjusting a delay amount of the strobe signal (DQS) in a plurality of steps in accordance with the set frequency of the clock signal (CK). The second adjustment circuit is capable of adjusting the delay amount of the strobe signal (DQS) with a higher precision than the first adjustment circuit.

Abstract: An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal (CK) and receives a data signal (DQ) and a strobe signal (DQS) from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal (DQS). The delay circuit includes a first adjustment circuit and a second adjustment circuit connected in series with the first adjustment circuit. The first adjustment circuit is capable of adjusting a delay amount of the strobe signal (DQS) in a plurality of steps in accordance with the set frequency of the clock signal (CK). The second adjustment circuit is capable of adjusting the delay amount of the strobe signal (DQS) with a higher precision than the first adjustment circuit.

Abstract: An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal and receives a data signal and a strobe signal from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal. The delay circuit includes a first adjustment circuit and a second adjustment circuit connected in series with the first adjustment circuit. The first adjustment circuit is capable of adjusting a delay amount of the strobe signal in a plurality of steps in accordance with the set frequency of the clock signal. The second adjustment circuit is capable of adjusting the delay amount of the strobe signal with a higher precision than the first adjustment circuit.

Abstract: An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal and receives a data signal and a strobe signal from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal. The delay circuit includes a first adjustment circuit and a second adjustment circuit connected in series with the first adjustment circuit. The first adjustment circuit is capable of adjusting a delay amount of the strobe signal in a plurality of steps in accordance with the set frequency of the clock signal. The second adjustment circuit is capable of adjusting the delay amount of the strobe signal with a higher precision than the first adjustment circuit.

Abstract: A memory cell for an associative storage memory device includes a transmission gate which is rendered conductive or non-conductive in response to a potential on a word line for transferring information between an information hold circuit and a bit line or between the information hold circuit and an inverted bit line. Match line are precharged to ground and supply potentials, respectively, and, thereafter, a retrieval circuit compares information on the bit line or inverted bit line with information held in the information hold circuit and produces a control signal to control the potentials on the match lines in accordance with the result of comparison. After the match lines are precharged, a gating circuit is rendered conductive in response to potentials on output control line and inverted output control line to thereby couple the control signal to the match lines.

Abstract: A semiconductor logic circuit includes a number of gate circuits and a voltage supply. Each of the gate circuits includes a series circuit comprising the same number of transistors of one conductivity type connected in series, and a parallel circuit comprising the same number of transistors of a different conductivity type connected in parallel. The series and parallel circuits are connected in series between a voltage supply and ground. The semiconductor logic circuit includes the same number of input pins, and an output pin connected in common to all of the gate circuits. Each of the input pins is connected to a different one of the transistors in the series circuit and to a different one of the transistors in the parallel circuit of each of the gate circuits.