Patents by Inventor Mitsuhiro Higashiho
Mitsuhiro Higashiho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7085188Abstract: In a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of an internal signal for every operation mode by required minimum control, a control method thereof, and a control method of a semiconductor device, there are provided an address switching circuit 13 for propagating either a refresh address ADD (Ref) from a refresh counter 14 at a time of a refresh mode or an external address ADD (R/W) at a time of data-input/output mode as internal address ADD (INT), a mode discriminating circuit 11 for discriminating between a refresh operation requesting signal REQ (Ref) and a data input/output requesting signal REQ (R/W) and for outputting a mode discriminating signal M, and a switch holding circuit 12 for outputting a switch change-over signal SW in accordance with the mode discriminating signal M, and the connection of the address switching circuit 13 is switched only at a time of a mode change.Type: GrantFiled: October 24, 2005Date of Patent: August 1, 2006Assignee: Fujitsu LimitedInventor: Mitsuhiro Higashiho
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Patent number: 7035156Abstract: In a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of an internal signal for every operation mode by required minimum control, a control method thereof, and a control method of a semiconductor device, there are provided an address switching circuit 13 for propagating either a refresh address ADD (Ref) from a refresh counter 14 at a time of a refresh mode or an external address ADD (R/W) at a time of data-input/output mode as internal address ADD (INT), a mode discriminating circuit 11 for discriminating between a refresh operation requesting signal REQ (Ref) and a data input/output requesting signal REQ (R/W) and for outputting a mode discriminating signal M, and a switch holding circuit 12 for outputting a switch change-over signal SW in accordance with the mode discriminating signal M, and the connection of the address switching circuit 13 is switched only at a time of a mode change.Type: GrantFiled: July 10, 2003Date of Patent: April 25, 2006Assignee: Fujitsu LimitedInventor: Mitsuhiro Higashiho
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Publication number: 20060039223Abstract: In a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of an internal signal for every operation mode by required minimum control, a control method thereof, and a control method of a semiconductor device, there are provided an address switching circuit 13 for propagating either a refresh address ADD (Ref) from a refresh counter 14 at a time of a refresh mode or an external address ADD (R/W) at a time of data-input/output mode as internal address ADD (INT), a mode discriminating circuit 11 for discriminating between a refresh operation requesting signal REQ (Ref) and a data input/output requesting signal REQ (R/W) and for outputting a mode discriminating signal M, and a switch holding circuit 12 for outputting a switch change-over signal SW in accordance with the mode discriminating signal M, and the connection of the address switching circuit 13 is switched only at a time of a mode change.Type: ApplicationFiled: October 24, 2005Publication date: February 23, 2006Inventor: Mitsuhiro Higashiho
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Patent number: 6795363Abstract: There are provided a semiconductor memory device and a refresh control method thereof to realize a refresh operation without any problem for external accesses while realizing low current dissipation operations for executing the refresh operation in separation from external access operation, in which the refresh operation is inhibited during execution of the external accesses. During this period, the internal operation in the refresh operation is controlled for the first refresh-operation-start request, but the internal operation for the second and subsequent refresh operation start requests is inhibited. Even when a plurality of refresh-operation-start requests are outputted previously while the refresh operation is inhibited during the external access operation, only the internal operation is not executed previously and the refresh operations after completion of the external access operation can surely be executed.Type: GrantFiled: October 1, 2002Date of Patent: September 21, 2004Assignee: Fujitsu LimitedInventors: Masami Nakashima, Mitsuhiro Higashiho
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Publication number: 20040179415Abstract: In a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of an internal signal for every operation mode by required minimum control, a control method thereof, and a control method of a semiconductor device, there are provided an address switching circuit 13 for propagating either a refresh address ADD (Ref) from a refresh counter 14 at a time of a refresh mode or an external address ADD (R/W) at a time of data-input/output mode as internal address ADD (INT), a mode discriminating circuit 11 for discriminating between a refresh operation requesting signal REQ (Ref) and a data input/output requesting signal REQ (R/W) and for outputting a mode discriminating signal M, and a switch holding circuit 12 for outputting a switch change-over signal SW in accordance with the mode discriminating signal M, and the connection of the address switching circuit 13 is switched only at a time of a mode change.Type: ApplicationFiled: July 10, 2003Publication date: September 16, 2004Applicant: FUJITSU LIMITEDInventor: Mitsuhiro Higashiho
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Patent number: 6633505Abstract: In a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of an internal signal for every operation mode by required minimum control, a control method thereof, and a control method of a semiconductor device, there are provided an address switching circuit 13 for propagating either a refresh address ADD (Ref) from a refresh counter 14 at a time of a refresh mode or an external address ADD (R/W) at a time of data-input/output mode as internal address ADD (INT), a mode discriminating circuit 11 for discriminating between a refresh operation requesting signal REQ (Ref) and a data input/output requesting signal REQ (R/W) and for outputting a mode discriminating signal M, and a switch holding circuit 12 for outputting a switch change-over signal SW in accordance with the mode discriminating signal M, and the connection of the address switching circuit 13 is switched only at a time of a mode change.Type: GrantFiled: April 26, 2002Date of Patent: October 14, 2003Assignee: Fujitsu LimitedInventor: Mitsuhiro Higashiho
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Patent number: 6618310Abstract: In a synchronous semiconductor memory device which provides the refresh cycle optimum for charge retention characteristics without being influenced by production variations, and without requiring much test time to measure characteristics before adjustment of the refresh time, and enables reduction of current consumption in a refresh operation, an output signal from an active pointer circuit which is a phase comparison signal from a DLL circuit is output as a digital signal, and the digital signal is converted by a D/A converter circuit to an analog signal for determining the current value of a constant current circuit, and then, in a measured cycle modification circuit constituting the constant current circuit, the current value responsive to the voltage value of this analog signal is set as the driving current of an oscillation circuit which is a refresh cycle measurement circuit so as to control a driving capability, thereby an oscillation signal for self-refreshing is output.Type: GrantFiled: July 19, 2001Date of Patent: September 9, 2003Assignee: Fujitsu LimitedInventors: Mitsuhiro Higashiho, Hajime Sato
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Publication number: 20030112688Abstract: There are provided a semiconductor memory device and a refresh control method thereof to realize a refresh operation without any problem for external accesses while realizing low current dissipation operations for executing the refresh operation in separation from external access operation, in which the refresh operation is inhibited during execution of the external accesses. During this period, the internal operation in the refresh operation is controlled for the first refresh-operation-start request, but the internal operation for the second and subsequent refresh operation start requests is inhibited. Even when a plurality of refresh-operation-start requests are outputted previously while the refresh operation is inhibited during the external access operation, only the internal operation is not executed previously and the refresh operations after completion of the external access operation can surely be executed.Type: ApplicationFiled: October 1, 2002Publication date: June 19, 2003Applicant: FUJITSU LIMITEDInventors: Masami Nakashima, Mitsuhiro Higashiho
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Publication number: 20030086324Abstract: In a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of an internal signal for every operation mode by required minimum control, a control method thereof, and a control method of a semiconductor device, there are provided an address switching circuit 13 for propagating either a refresh address ADD (Ref) from a refresh counter 14 at a time of a refresh mode or an external address ADD (R/W) at a time of data-input/output mode as internal address ADD (INT), a mode discriminating circuit 11 for discriminating between a refresh operation requesting signal REQ (Ref) and a data input/output requesting signal REQ (R/W) and for outputting a mode discriminating signal M, and a switch holding circuit 12 for outputting a switch change-over signal SW in accordance with the mode discriminating signal M, and the connection of the address switching circuit 13 is switched only at a time of a mode change.Type: ApplicationFiled: April 26, 2002Publication date: May 8, 2003Applicant: FUJITSU LIMITEDInventor: Mitsuhiro Higashiho
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Patent number: 6542417Abstract: A semiconductor memory operates in a write mode and a read mode. The memory includes memory cells, pairs of bit lines connected to the memory cells, sense amplifiers having first and second I/O terminals connected to the bit lines, column selection gates connected to the associated sense amplifiers, and a control circuit. The control circuit controls the sense amplifiers and the column selection gate, so that selected column selection gate turns on before the sense amplifiers are activated during the write mode. The write data is applied to the first I/O terminals of the sense amplifiers. The semiconductor memory thus produced according to the present invention has a reduced circuit size.Type: GrantFiled: January 17, 2001Date of Patent: April 1, 2003Assignee: Fujitsu LimitedInventor: Mitsuhiro Higashiho
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Patent number: 6512717Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.Type: GrantFiled: July 29, 1996Date of Patent: January 28, 2003Assignee: Fujitsu LimitedInventors: Satoshi Eto, Masato Matsumiya, Shusaku Yamaguchi, Toshikazu Nakamura, Hideki Kano, Ayako Kitamoto, Mitsuhiro Higashiho
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Publication number: 20020054525Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.Type: ApplicationFiled: July 29, 1996Publication date: May 9, 2002Inventors: SATOSHI ETO, MASATO MATSUMIYA, SHUSAKU YAMAGUCHI, TOSHIKAZU NAKAMURA, HIDEKI KANO, AYAKO KITAMOTO, MITSUHIRO HIGASHIHO
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Publication number: 20020051396Abstract: In a synchronous semiconductor memory device which provides the refresh cycle optimum for charge retention characteristics without being influenced by production variations, and without requiring much test time to measure characteristics before adjustment of the refresh time, and enables reduction of current consumption in a refresh operation, an output signal from an active pointer circuit which is a phase comparison signal from a DLL circuit is output as a digital signal, and the digital signal is converted by a D/A converter circuit to an analog signal for determining the current value of a constant current circuit, and then, in a measured cycle modification circuit constituting the constant current circuit, the current value responsive to the voltage value of this analog signal is set as the driving current of an oscillation circuit which is a refresh cycle measurement circuit so as to control a driving capability, thereby an oscillation signal for self-refreshing is output.Type: ApplicationFiled: July 19, 2001Publication date: May 2, 2002Applicant: FUJITSU LIMITEDInventors: Mitsuhiro Higashiho, Hajime Sato
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Patent number: 6377101Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.Type: GrantFiled: February 22, 2000Date of Patent: April 23, 2002Assignee: Fujitsu LimitedInventors: Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima
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Publication number: 20020027829Abstract: A synchronous semiconductor memory apparatus is capable of activating an input buffer circuit only in a required operating cycle and achieving low current consumption without degrading high speed response properties of an input buffer. When combination of control signals (Control) such as ICS, /RAS, /CAS, /WE and the like is directed to active command (ACTV), read command (READ, READA), write command (WRITE, WRITEA), mode register command (MRS), pre-charge command (PRE) and the like, a latch operation is dynamically performed for input from address pins. In this way, in the case where a signal iRAS is set at a low level, a latch signal aCLK is output to the rising edge of a signal iCLK, thereby latching addresses Add or the like. Alternatively, in the case where a signal iRAS or iCAS is set at a low level, the latch signal aCLK is output to the rising edge of the signal iCLK, thereby latching addresses Add or the like.Type: ApplicationFiled: July 16, 2001Publication date: March 7, 2002Applicant: FUJITSU LIMITEDInventors: Mitsuhiro Higashiho, Shigemasa Ito
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Patent number: 6351432Abstract: A synchronous semiconductor memory apparatus is capable of activating an input buffer circuit only in a required operating cycle and achieving low current consumption without degrading high speed response properties of an input buffer. When combination of control signals (Control) such as /CS, /RAS, /CAS, /WE and the like is directed to active command (ACTV), read command (READ, READA), write command (WRITE, WRITEA), mode register command (MRS), pre-charge command (PRE) and the like, a latch operation is dynamically performed for input from address pins. In this way, in the case where a signal iRAS is set at a low level, a latch signal aCLK is output to the rising edge of a signal iCLK, thereby latching addresses Add or the like. Alternatively, in the case where a signal iRAS or iCAS is set at a low level, the latch signal aCLK is output to the rising edge of the signal iCLK, thereby latching addresses Add or the like.Type: GrantFiled: July 16, 2001Date of Patent: February 26, 2002Assignee: Fujitsu LimitedInventors: Mitsuhiro Higashiho, Shigemasa Ito
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Publication number: 20020021157Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.Type: ApplicationFiled: February 22, 2000Publication date: February 21, 2002Inventors: Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima
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Publication number: 20010008492Abstract: A semiconductor memory operates in a write mode and a read mode. The memory includes memory cells, pairs of bit lines connected to the memory cells, sense amplifiers having first and second I/O terminals connected to the bit lines, column selection gates connected to the associated sense amplifiers, and a control circuit. The control circuit controls the sense amplifiers and the column selection gate, so that selected column selection gate turns on before the sense amplifiers are activated during the write mode. The write data is applied to the first I/O terminals of the sense amplifiers. The semiconductor memory thus produced according to the present invention has a reduced circuit size.Type: ApplicationFiled: January 17, 2001Publication date: July 19, 2001Applicant: FUJITSU LIMITEDInventor: Mitsuhiro Higashiho
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Patent number: 6111802Abstract: A semiconductor memory device includes a memory cell connected to a bit line and a word line, a bit line precharge circuit which precharges the bit line to a ground voltage, and a word decoder which sets the word line to a negative voltage when the word line is not selected.Type: GrantFiled: May 1, 1998Date of Patent: August 29, 2000Assignee: Fujitsu LimitedInventors: Hideki Kano, Masato Matsumiya, Masato Takita, Toru Koga, Satoshi Eto, Toshikazu Nakamura, Mitsuhiro Higashiho, Kuninori Kawabata, Ayako Kitamoto
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Patent number: 6049239Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.Type: GrantFiled: September 22, 1997Date of Patent: April 11, 2000Assignee: Fujitsu LimitedInventors: Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima