Patents by Inventor Mitsuhiro Tanaka

Mitsuhiro Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120168771
    Abstract: A semiconductor device is provided such that a reverse leak current is suppressed, and a Schottky junction is reinforced. The semiconductor device includes an epitaxial substrate formed by laminating a group of group-III nitride layers on a base substrate in such a manner that (0001) surfaces of said group-III nitride layers are substantially parallel to a substrate surface, and a Schottky electrode, in which the epitaxial substrate includes a channel layer formed of a first group-III nitride having a composition of Inx1Aly1Gaz1N, a barrier layer formed of a second group-III nitride having a composition of Inx2Aly2N, and a contact layer formed of a third group-III nitride having insularity and adjacent to the barrier layer, and the Schottky electrode is connected to the contact layer. In addition, a heat treatment is performed under a nitrogen atmosphere after the gate electrode has been formed.
    Type: Application
    Filed: March 8, 2012
    Publication date: July 5, 2012
    Inventors: Makoto Miyoshi, Shigeaki Sumiya, Mikiya Ichimura, Tomohiko Sugiyama, Mitsuhiro Tanaka
  • Publication number: 20120161152
    Abstract: Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes a (111) single crystal Si substrate, a buffer layer, and a crystal layer. The buffer layer is formed of a first lamination unit and a second lamination unit being alternately laminated. The first lamination unit includes a composition modulation layer and a first intermediate layer. The composition modulation layer is formed of a first unit layer and a second unit layer having different compositions being alternately and repeatedly laminated so that a compressive strain exists therein. The first intermediate layer enhances the compressive strain existing in the composition modulation layer. The second lamination unit is a second intermediate layer that is substantially strain-free.
    Type: Application
    Filed: March 7, 2012
    Publication date: June 28, 2012
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto MIYOSHI, Shigeaki Sumiya, Mikiya Ichimura, Sota Maehara, Mitsuhiro Tanaka
  • Publication number: 20120126293
    Abstract: An epitaxial substrate, in which a group of group-III nitride layers is formed on a single-crystal silicon substrate so that a crystal plane is approximately parallel to a substrate surface, comprises: a first group-III nitride layer formed of AlN on the base substrate; a second group-III nitride layer formed of InxxAlyyGazzN (xx+yy+zz=1, 0?xx?1, 0<yy?1 and 0<zz?1) on the first group-III nitride layer; and at least one third group-III nitride layer epitaxially-formed on the second group-III nitride layer, wherein: the first group-III nitride layer is a layer containing multiple defects including at least one type of a columnar crystal, a granular crystal, a columnar domain and a granular domain; and an interface between the first group-III nitride layer and the second group-III nitride layer is a three-dimensional asperity surface.
    Type: Application
    Filed: January 19, 2012
    Publication date: May 24, 2012
    Applicant: NGK INSULATORS, LTD.
    Inventors: Shigeaki Sumiya, Makoto Miyoshi, Tomohiko Sugiyama, Mikiya Ichimura, Yoshitaka Kuraoka, Mitsuhiro Tanaka
  • Patent number: 8107242
    Abstract: A substrate includes a pair of surfaces opposing to each other in a direction. First electronic components are provided on one surface. Second electronic components lower than a maximum value of the height of the first electronic components in a direction are provided on the other surface. Insulating resin includes a covering part adhering and covering the second electronic components and the other surface, and side surface part extending from the periphery of the substrate to a side of the second electronic components along the direction. A lid covers the first electronic components from an opposite side of the substrate, and is fixed to the side surface part from the opposite side of the substrate.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: January 31, 2012
    Assignee: Daikin Industries, Ltd,
    Inventors: Akio Yoshimoto, Mitsuhiro Tanaka
  • Patent number: 8093601
    Abstract: In an active matrix substrate (100) of the present invention, a gate bus line (105) and a gate electrode (166) extend in the first direction (the x direction). At a contact portion (168) for electrically connecting the gate bus line (105) with the drain regions of a first-conductivity-type transistor section (162) and a second-conductivity-type transistor section (164), the direction of the straight line (L1) of the shortest distance (d1) between one of a plurality of first-conductivity-type drain connecting portions (168c) that is closest to the gate bus line (105) and the gate bus line (105) is inclined with respect to the second direction (the y direction).
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: January 10, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tadayoshi Miyamoto, Mitsuhiro Tanaka
  • Patent number: 8026718
    Abstract: An aspect of the present invention provides a magnetic sensor which is operated better at a high temperature range not lower than 300° C. compared with a conventional magnetic sensor. A operating layer having a heterojunction interface is formed by laminating a first layer made of GaN whose electron concentration is not more than 1×1016/cm3 at room temperature and a second layer made of AlxGa1-xN (0<x?0.3). Therefore, in a two-dimensional electron gas region, carrier mobility is further enhanced while a carrier concentration is further lowered. Accordingly, there is realized a Hall element which can be used with measurement sensitivity similar to that at room temperature by constant-current drive even at a high temperature, while having the high measurement sensitivity in both the constant-current drive and constant-voltage drive at room temperature.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: September 27, 2011
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Mitsuhiro Tanaka
  • Patent number: 8008689
    Abstract: A normally-off operation type HEMT device excellent in characteristics can be realized. A two-dimensional electron gas region is formed in a periphery of a hetero-junction interface of a base layer and a barrier layer, so that access resistance in an access portion, that is, between a drain and a gate and between a gate and a source is sufficiently lowered, and at the same time, a P-type region is formed immediately under the gate. This realizes a normally-off type HEMT device having a low on-resistance. Further, when a film thickness of an insulating layer is defined as t (nm) and a relative permittivity of a substance forming the insulating layer is defined as k, a threshold voltage as high as +3 V or more can be attained by satisfying k/t?0.85 (nm?1).
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: August 30, 2011
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Mitsuhiro Tanaka
  • Publication number: 20110203773
    Abstract: A cooling member includes a heat-transfer member having a groove and a refrigerant introducing pipe pressed into the groove. The refrigerant introducing pipe has a pressed region positioned inwardly of the edge of the heat-transfer member, and at least one curbed surface portion. A method for manufacturing a cooling member includes preparing a punch having at least one curved corner and a pressing surface, positioning the corner, and moving the punch closer to the groove to press the refrigerant introducing pipe into the groove with the pressing surface. A device for manufacturing a cooling member includes the punch and a support configured to support the heat-transfer member so the groove is positioned opposite the punch.
    Type: Application
    Filed: November 2, 2009
    Publication date: August 25, 2011
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Junichi Teraki, Mitsuhiro Tanaka, Noriyuki Okuda
  • Patent number: 7982241
    Abstract: A buffer layer formed of Inx1Aly1Gaz1N formed on a base, with an upper part of the buffer layer containing columnar polycrystalline including a grain boundary existing in a direction substantially perpendicular to a surface of the base. The number of grain boundaries in the lower part of the buffer layer is greater than that in the upper part, and a full width at half maximum of an X-ray rocking curve of the upper part is 300-3000 seconds, RMS of the surface of the buffer layer is 0.2 nm-6 nm, and the ratio of the grain boundary width of the crystal grain of the upper part in a direction parallel to the base surface to the formation thickness of the buffer layer is 0.5-1.5.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: July 19, 2011
    Assignee: NGK Insulators, Ltd.
    Inventors: Yoshitaka Kuraoka, Makoto Miyoshi, Shigeaki Sumiya, Mitsuhiro Tanaka
  • Patent number: 7955437
    Abstract: An apparatus for fabricating a III-V nitride film by a MOCVD method, including a reactor prepared horizontally, a susceptor to hold a substrate thereon installed in the reactor, a heater to heat the substrate to a predetermined temperature via the susceptor, and a cooling mechanism to directly cool down at least the portion of the inner wall of the reactor opposite to the substrate.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: June 7, 2011
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomohiko Shibata, Yukinori Nakamura, Mitsuhiro Tanaka
  • Publication number: 20110062493
    Abstract: Provided is an epitaxial substrate for semiconductor device that is capable of achieving a semiconductor device having high reliability in reverse characteristics of schottky junction. An epitaxial substrate for semiconductor device obtained by forming, on a base substrate, a group of group III nitride layers by lamination such that a (0001) crystal plane of each layer is approximately parallel to a substrate surface includes: a channel layer formed of a first group III nitride having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1, z1>0); and a barrier layer formed of a second group III nitride having a composition of Inx2Aly2N (x2+y2=1, x2>0, y2>0), wherein the second group III nitride is a short-range-ordered mixed crystal having a short-range order parameter ? satisfying a range where 0???1.
    Type: Application
    Filed: August 10, 2010
    Publication date: March 17, 2011
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto MIYOSHI, Yoshitaka KURAOKA, Shigeaki SUMIYA, Mikiya ICHIMURA, Tomohiko SUGIYAMA, Mitsuhiro TANAKA
  • Publication number: 20110049570
    Abstract: Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent ohmic contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of Inx1Aly1Gaz1N (x1+y1+z1=1) is formed. On the channel layer, a barrier layer formed of a second group III nitride that contains at least In and Al and has a composition of Inx2Aly2Gaz2N (x2+y2+z2=1) is formed such that an In composition ratio of a near-surface portion is larger than an In composition ratio of a portion other than the near-surface portion.
    Type: Application
    Filed: August 10, 2010
    Publication date: March 3, 2011
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Yoshitaka Kuraoka, Shigeaki Sumiya, Mikiya Ichimura, Tomohiko Sugiyama, Mitsuhiro Tanaka
  • Publication number: 20110049571
    Abstract: Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent schottky contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of Inx1Aly1Gaz1N (x1+y1+z1=1) is formed. On the channel layer, a barrier layer formed of a second group III nitride that contains at least In and Al and has a composition of Inx2Aly2Gaz2N (x2+y2+z2=1) is formed such that an In composition ratio of a near-surface portion is smaller than an In composition ratio of a portion other than the near-surface portion.
    Type: Application
    Filed: August 13, 2010
    Publication date: March 3, 2011
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto MIYOSHI, Yoshitaka Kuraoka, Shigeaki Sumiya, Mikiya Ichimura, Tomohiko Sugiyama, Mitsuhiro Tanaka
  • Publication number: 20110024796
    Abstract: Provided is an epitaxial substrate having excellent two-dimensional electron gas characteristics and reduced internal stress due to strains. A channel layer is formed of a first group III nitride represented by Inx1Aly1Gaz1N (x1+y1+z1=1) so as to have a composition in a range determined by x1=0 and 0?y1?0.3. A barrier layer is formed of a second group III nitride represented by Inx2Aly2Gaz2N (x2+y2+z2=1) so as to have a composition, in a ternary phase diagram with InN, AlN and GaN being vertices, in a range surrounded by five straight lines determined in accordance with the composition (AlN molar fraction) of the first group III nitride.
    Type: Application
    Filed: September 17, 2010
    Publication date: February 3, 2011
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Yoshitaka Kuraoka, Shigeaki Sumiya, Mitsuhiro Tanaka
  • Publication number: 20110024795
    Abstract: Provided is an epitaxial substrate capable of manufacturing a HEMT device that has excellent two-dimensional electron gas characteristics and is capable of performing normally-off operation. A channel layer is formed of a first group III nitride represented by Inx1Aly1Gaz1N (x1+y1+z1=1) so as to have a composition in a range determined by x1=0 and 0?y1?0.3. A barrier layer is formed of a second group III nitride represented by Inx2Aly2Gaz2N (x2+y2+z2=1) so as to have a composition, in a ternary phase diagram with InN, AlN and GaN being vertices, in a range surrounded by four straight lines determined in accordance with the composition (AlN molar fraction) of the first group III nitride and to have a thickness of 5 nm or less.
    Type: Application
    Filed: September 17, 2010
    Publication date: February 3, 2011
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Yoshitaka Kuraoka, Shigeaki Sumiya, Mitsuhiro Tanaka
  • Publication number: 20100289029
    Abstract: An epitaxial substrate having preferable two dimensional electron gas characteristic and contact characteristic is provided in the present invention. A channel layer is formed on a base substrate with GaN. A spacer layer is formed on the channel layer with AlN. A barrier layer is formed on the spacer layer with group III nitride having a composition of InXAlyGazN (wherein x+y+z=1) and at least including In, Al, and Ga such that the composition of the barrier layer is within the range surrounded with four lines defined in accordance with the composition on a ternary phase diagram with InN, AlN, and GaN as vertexes.
    Type: Application
    Filed: April 26, 2010
    Publication date: November 18, 2010
    Applicant: NGK Insulators, Ltd.
    Inventors: Mikiya ICHIMURA, Makoto Miyoshi, Mitsuhiro Tanaka
  • Patent number: 7825417
    Abstract: A technique for suppressing the bowing of an epitaxial wafer is provided. The epitaxial wafer is prepared by successively epitaxially growing a target group III-nitride layer, an interlayer and another group III-nitride layer on a substrate with a buffer layer. The interlayer is mainly composed of a mixed crystal of GaN and InN expressed in a general formula (GaxIny)N (0?x?1, 0?y?1, x+y=1) (or a crystal of GaN), and does not contain Al. The interlayer is epitaxially formed at a lower growth temperature than those of the group III-nitride layers, more specifically at a temperature in a range of at least 350° C. to not more than 1000° C.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: November 2, 2010
    Assignee: NGK Insulators, Ltd.
    Inventors: Masahiro Sakai, Mitsuhiro Tanaka, Takashi Egawa
  • Publication number: 20100177483
    Abstract: A substrate includes a pair of surfaces opposing to each other in a direction. First electronic components are provided on one surface. Second electronic components lower than a maximum value of the height of the first electronic components in a direction are provided on the other surface. Insulating resin includes a covering part adhering and covering the second electronic components and the other surface, and side surface part extending from the periphery of the substrate to a side of the second electronic components along the direction. A lid covers the first electronic components from an opposite side of the substrate, and is fixed to the side surface part from the opposite side of the substrate.
    Type: Application
    Filed: May 29, 2008
    Publication date: July 15, 2010
    Inventors: Akio Yoshimoto, Mitsuhiro Tanaka
  • Publication number: 20100078679
    Abstract: Provided is a light-receiving device which has light-receiving sensitivity superior to that of a conventional Schottky diode type light-receiving device and also has sufficiently-strengthened junction of a Schottky electrode. A first contact layer formed of AlGaN and having conductivity, a light-receiving layer formed of AlGaN, and a second contact layer formed of AlN and having a thickness of 5 nm are epitaxially formed on a predetermined substrate in the stated order, and a second electrode is brought into Schottky junction with the second contact layer, to thereby form MIS junction. Further, after the Schottky junction, heat treatment is performed under a nitrogen gas atmosphere at 600° C. for 30 seconds.
    Type: Application
    Filed: August 19, 2009
    Publication date: April 1, 2010
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto MIYOSHI, Mitsuhiro Tanaka
  • Publication number: 20100072493
    Abstract: In an active matrix substrate (100) of the present invention, a gate bus line (105) and a gate electrode (166) extend in the first direction (the x direction). At a contact portion (168) for electrically connecting the gate bus line (105) with the drain regions of a first-conductivity-type transistor section (162) and a second-conductivity-type transistor section (164), the direction of the straight line (L1) of the shortest distance (d1) between one of a plurality of first-conductivity-type drain connecting portions (168c) that is closest to the gate bus line (105) and the gate bus line (105) is inclined with respect to the second direction (the y direction).
    Type: Application
    Filed: September 25, 2007
    Publication date: March 25, 2010
    Inventors: Tadayoshi Miyamoto, Mitsuhiro Tanaka