Patents by Inventor Mitsuji Nunokawa

Mitsuji Nunokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9824939
    Abstract: A semiconductor device having a composite pad including a primary portion and a subsidiary portion is disclosed. The primary portion is provided for electrical connection to an internal circuit of the semiconductor device. The subsidiary portion is provided for probing, in particular, for testing high frequency performance of the semiconductor device by probing with a RF-probe. Because the subsidiary portion is independent from the primary portion, the subsidiary portion does not affect the electrical performance of the semiconductor device. Also, the subsidiary portion has a narrowed contact area with respect to the RF-probe to lessen adherence of metal flakes from the pad onto the probe.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 21, 2017
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Mitsuji Nunokawa
  • Publication number: 20160293499
    Abstract: A semiconductor device having a composite pad including a primary portion and a subsidiary portion is disclosed. The primary portion is provided for the electrical connection to the internal circuit of the semiconductor device. While, the subsidiary portion is provided for the probing, in particular, for testing high frequency performance of the semiconductor device by probing the RF-probe. Because the subsidiary portion is independent from the primary portion, the subsidiary portion causes no effect in the electrical performance of the semiconductor device. Also, the subsidiary portion with a narrowed contact area with respect to the RF-probe leaves lesser flakes of the pad onto the probe.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 6, 2016
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Mitsuji NUNOKAWA
  • Patent number: 7855450
    Abstract: In a circuit module for a high frequency, a resistance film is formed on a side of a semiconductor circuit chip, mounted above a dielectric substrate through ground metal layers, opposite to the dielectric substrate. A distance from the ground metal layer to the resistance film is a ¼ wavelength at a predetermined frequency, and the resistance film has a sheet resistance equal to a characteristic impedance of air. A second dielectric substrate with the metal layer formed on a side opposite to the resistance film can be mounted. When being adhered to the second dielectric substrate, the resistance film has a characteristic impedance determined by a permittivity of a material of the semiconductor circuit chip. When being formed in space from the semiconductor circuit chip, the resistance film has a sheet resistance equal to a characteristic impedance of air. The thickness of the second dielectric substrate is a ¼ wavelength in a desired frequency.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: December 21, 2010
    Assignees: Fujitsu Limited, Eudyna Devices, Inc.
    Inventors: Toshihiro Shimura, Yoji Ohashi, Mitsuji Nunokawa
  • Patent number: 7550831
    Abstract: An electronic device has a substrate, a conductive layer and a substrate mounted portion. The substrate has a circuit portion used from 60 GHz to 80 GHz. The conductive layer is provided directly on a face of the substrate that is opposite side of the circuit portion. The face having the circuit portion of the substrate is mounted face down on the substrate mounted portion. A thickness of the conductive layer is a thickness where a sheet resistance of the conductive layer is ¼ to 4 times of a resistance component of an impedance of the substrate.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: June 23, 2009
    Assignee: Eudyna Devices Inc.
    Inventor: Mitsuji Nunokawa
  • Publication number: 20070138622
    Abstract: An electronic device has a substrate, a conductive layer and a substrate mounted portion. The substrate has a circuit portion used from 60 GHz to 80 GHz. The conductive layer is provided directly on a face of the substrate that is opposite side of the circuit portion. The face having the circuit portion of the substrate is mounted face down on the substrate mounted portion. A thickness of the conductive layer is a thickness where a sheet resistance of the conductive layer is ¼ to 4 times of a resistance component of an impedance of the substrate.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 21, 2007
    Applicant: EUDYNA DEVICES INC.
    Inventor: Mitsuji Nunokawa
  • Publication number: 20070132094
    Abstract: In a circuit module for a high frequency, a resistance film is formed on a side of a semiconductor circuit chip, mounted above a dielectric substrate through ground metal layers, opposite to the dielectric substrate. A distance from the ground metal layer to the resistance film is a ¼ wavelength at a predetermined frequency, and the resistance film has a sheet resistance equal to a characteristic impedance of air. A second dielectric substrate with the metal layer formed on a side opposite to the resistance film can be mounted. When being adhered to the second dielectric substrate, the resistance film has a characteristic impedance determined by a permittivity of a material of the semiconductor circuit chip. When being formed in space from the semiconductor circuit chip, the resistance film has a sheet resistance equal to a characteristic impedance of air. The thickness of the second dielectric substrate is a ¼ wavelength in a desired frequency.
    Type: Application
    Filed: March 30, 2006
    Publication date: June 14, 2007
    Inventors: Toshihiro Shimura, Yoji Ohashi, Mitsuji Nunokawa
  • Patent number: 6642099
    Abstract: There is provided a compound semiconductor device having a capacitor, to prevent a leakage current flowing between an upper electrode and a lower electrode of the capacitor via an insulating protective film. The compound semiconductor device comprises a first electrode of a capacitor formed on a compound semiconductor substrate via a first insulating film, a dielectric film of the capacitor formed on the first electrode, a second electrode of a capacitor formed on the dielectric film, a second insulating film for covering an upper surface and side surfaces of the second electrode, and an insulating protective film for covering the second insulating film, the dielectric film, the first electrode and the first insulating film, and having a hydrogen containing rate which is larger than the second insulating film.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: November 4, 2003
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Kenji Arimochi, Tsutom Igarashi, Mitsuji Nunokawa
  • Publication number: 20020130389
    Abstract: There is provided a compound semiconductor device having a capacitor, to prevent a leakage current flowing between an upper electrode and a lower electrode of the capacitor via an insulating protective film. The compound semiconductor device comprises a first electrode of a capacitor formed on a compound semiconductor substrate via a first insulating film, a dielectric film of the capacitor formed on the first electrode, a second electrode of a capacitor formed on the dielectric film, a second insulating film for covering an upper surface and side surfaces of the second electrode, and an insulating protective film for covering the second insulating film, the dielectric film, the first electrode and the first insulating film, and having a hydrogen containing rate which is larger than the second insulating film.
    Type: Application
    Filed: May 7, 2002
    Publication date: September 19, 2002
    Applicant: Fujitsu Quantum Devices Limited
    Inventors: Kenji Arimochi, Tsutom Igarashi, Mitsuji Nunokawa
  • Patent number: 6404004
    Abstract: There is provided a compound semiconductor device having a capacitor, to prevent a leakage current flowing between an upper electrode and a lower electrode of the capacitor via an insulating protective film. The compound semiconductor device comprises a first electrode of a capacitor formed on a compound semiconductor substrate via a first insulating film, a dielectric film of the capacitor formed on the first electrode, a second electrode of a capacitor formed on the dielectric film, a second insulating film for covering an upper surface and side surfaces of the second electrode, and an insulating protective film for covering the second insulating film, the dielectric film, the first electrode and the first insulating film, and having a hydrogen containing rate which is larger than the second insulating film.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: June 11, 2002
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Kenji Arimochi, Tsutom Igarashi, Mitsuji Nunokawa
  • Patent number: 6214639
    Abstract: A method of producing a semiconductor device including a step of forming separation grooves in scribing regions defined at boundary portions between a plurality of semiconductor-device forming portions formed on a top surface of a semiconductor substrate; a step of defining portions of the scribing regions in the semiconductor substrate as substrate connecting portions; and a step of cutting off the substrate connecting portions along the separation grooves, to thereby separate the plurality of semiconductor-device forming portions into chips. These production steps contribute to a higher working efficiency in a later assembling process and to improved mass-production.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: April 10, 2001
    Assignee: Fujitsu Limited
    Inventors: Masaomi Emori, Mitsuji Nunokawa, Kenichi Hiratsuka, Masanori Ishii, Hiroshi Kawakubo
  • Patent number: 6146931
    Abstract: A semiconductor device includes an ohmic electrode and a Schottky electrode respectively carrying interconnection patterns with intervening adhesion layer and a diffusion barrier layer, wherein the Schottky electrode further includes a metal layer that prevents a reaction between the Schottky electrode and the diffusion barrier layer such that the metal layer is interposed between the top surface of the Schottky electrode and adhesion layer for increasing the distance between the diffusion barrier layer and the Schottky electrode.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Mitsuji Nunokawa, Yutaka Sato
  • Patent number: 6011281
    Abstract: A semiconductor device includes an ohmic electrode and a Schottky electrode respectively carrying interconnection patterns with intervening adhesion layer and a diffusion barrier layer, wherein the Schottky electrode further includes a metal layer that prevents a reaction between the Schottky electrode and the diffusion barrier layer such that the metal layer is interposed between the top surface of the Schottky electrode and adhesion layer for increasing the distance between the diffusion barrier layer and the Schottky electrode.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: January 4, 2000
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Mitsuji Nunokawa, Yutaka Sato
  • Patent number: 5876877
    Abstract: An optical exposure mask for patterning an optical beam comprises an etching stop layer of a material that is substantially transparent with respect to the optical beam, a transparent pattern provided on one of upper and lower major surfaces of the etching stop layer, and an opaque pattern provided on one of the upper and lower major surfaces of the etching stop layer for patterning the optical beam, wherein the material for the etching stop layer is selected from a group essentially consisted of Al.sub.2 O.sub.3, MgO and a mixture thereof, and the etching stop layer has an etching rate that is substantially smaller than the etching rate of a material forming the transparent pattern for any of dry and wet etching processes.
    Type: Grant
    Filed: December 27, 1991
    Date of Patent: March 2, 1999
    Assignee: Fujitsu Limited
    Inventors: Isamu Hanyu, Mitsuji Nunokawa, Satoru Asai
  • Patent number: 5418093
    Abstract: A projection exposure method includes the steps of (a) irradiating a light from a light source on an optical mask, where the optical mask includes a main space which transmits light and has a desired exposure pattern, and a subspace which transmits light and is provided adjacent to the main space, and (b) exposing a photoresist layer by the light which is transmitted through the optical mask via a lens so as to project an optical image of the main space, where the subspace has a narrow width such that the light transmitted through the subspace by itself does not expose the photosensitive layer.
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: May 23, 1995
    Assignee: Fujitsu Limited
    Inventors: Satoru Asai, Isamu Hanyu, Mitsuji Nunokawa