Abstract: A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator comprises first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also comprises a parallel-to-serial converter to successively selects the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.

Abstract: A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator comprises first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also comprises a parallel-to-serial converter to successively selects the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.

Abstract: A clock phase detecting circuit is provided which is arranged in a receiving section of a multiplex radio apparatus. Difference detecting unit detects the difference between input and output signals to and from an equalizing circuit, and squaring unit squares the detected difference. The squared value thus obtained shows a minimum value when the phase of a clock signal output from a clock regenerating circuit coincides with a normal position of signal point. Therefore, phase adjusting unit outputs a control signal to the clock regenerating circuit while monitoring the squared value, to adjust the phase of the clock signal output from the clock regenerating circuit so that the squared value output from the squaring unit may be minimized.

Abstract: A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator comprises first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also comprises a parallel-to-serial converter to successively selects the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.

Abstract: A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator includes first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also includes a parallel-to-serial converter to successively select the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.

Abstract: An echo canceller is disclosed which generates an echo replica based on a transmit signal to cancel an echo. The echo canceller includes a linear echo canceller circuit for generating an echo replica of the transmit signal in the absence of distortion. The echo canceller further includes a waveform-distortion compensation circuit, coupled with the linear echo canceller circuit, for generating an echo replica for compensating waveform distortion occurred in an echo response when the transmit signal is distorted. In the echo canceller, the echo is canceled by use of the echo replica generated in the linear echo canceller circuit in the absence of distortion in the transmit signal, and is canceled by use of the echo replica generated in the waveform-distortion compensation circuit when the transmit signal is distorted.

Abstract: A data receiving device for reproducing a received symbol from a received data signal, includes a timing recovery circuit for controlling a phase of sampling the received data signal, by using pre-cursor information, the timing recovery circuit produces sampling phase control information by eliminating a high frequency component for the pre-cursor information, accumulating eliminated output, comparing accumulated output with a positive or a negative threshold value and subtracting the threshold value from compared output. The data receiving device further includes a masking circuit for masking the sampling phase control information when no-signal data or frame is detected in the received data signal.

Abstract: A digital subscriber loop interface unit, connected to a digital subscriber loop, includes an echo canceler for carrying out a echo canceling operation, a decision feedback equalizer for carrying out an equalizing operation, and a transversal filter, provided in at least one of the echo canceler and the decision feedback equalizer, in which a plurality of taps among all taps are grouped into groups, each group including a predetermined number of taps continuously arranged, a single tap coefficient being assigned to the taps in each group. A digital subscriber loop interface unit may include an echo canceler for carrying out a echo canceling operation by using a value obtained by adding +1 to a symbol value represented by a 2B1Q code.

Abstract: The present invention provides, a two-system A/D converter, which provides a digital output signal with a higher conversion precision than is achieved by a single-system A/D converter. Conversely, by using a two-system D/A converter with a lower conversion precision, the present invention provides an analog output signal with a higher conversion precision than is achieved by a single-system D/A converter. Further, a digital signal clock changing unit produces data by performing high sampling of the first digital data trains, and the second digital data is synchronized with a second clock through an interpolation processing based on the timing difference between the first and second clocks. A high-precision A/D and D/A converter apparatus is thus realized by using two pulse code modulation coder/decoders (PCM.CODECs) and one digital signal processor (DSP) in a small, inexpensive structure.

Abstract: The present invention provides a two-system A/D converter, which provides a digital output signal with a higher conversion precision than is achieved by a single-system A/D converter. Conversely, by using a two-system D/A converter with a lower conversion precision, the present invention provides an analog output signal with a higher conversion precision than is achieved by a single-system D/A converter. Further, a digital signal clock changing unit produces data by performing high sampling of the first digital data trains, and the second digital data is synchronized with a second clock through an interpolation processing based on the timing difference between the first and second clocks. A high-precision A/D and D/A converter apparatus is thus realized by using two pulse code modulation coder/decoders (PCM.CODECs) and one digital signal processor (DSP).

Abstract: A digital adaptive equalizer equalizes received signals through digital filtering operations by changing filtering coefficients. It comprises a coefficient calculating unit for calculating the filtering coefficients by using one kind of parameters, such as distance, as an input to a function corresponding to the filtering coefficients and a filtering operation executing unit for executing digital filtering operations based on the filtering coefficients. A variable lag filter for adjusting the phase delay of received received signals is provided. A coefficient converting unit calculates a part or all of tap coefficients of the filter using at least one piece of timing control information.

Abstract: An input analog signal having a periodicity is converted into one-bit digital signals by an A/D converter (42), and the one-bit digital signals are converted into parallel signals by a serial-to-parallel converter (43). A correlation between the parallel signals and a reference signal string is detected by a correlation device (45). When the correlation is detected, a hold circuit (48) holds detection of the correlation and hence outputs a tone signal detection result. With the above simple, low power consumption circuit structure, the tone signal can be detected.

Abstract: A digital loop filter includes a first loop filter for generating first phase control information at variable time intervals on the basis of phase error information indicating a phase difference between a first signal and a second signal. A second loop filter detects a frequency deviation between the first and second signals from the phase error information and generates second phase control information with a period inversely proportional to the frequency deviation. An adder generates finalized phase control information obtained by adding the first phase control information and the second phase control information to each other.

Abstract: The invention provides a digital PLL circuit wherein the integration time constant of a random walk filter can be varied adaptively in response to a frequency error. A master clock signal having a frequency equal to N (integral number) times that of an input clock signal is normally divided by N by a divider, and the division output of the divider and the input clock signal are compared in phase with each other by a phase comparator. The dividing ratio of the divider is temporarily varied in accordance with a result of the comparison so as to make the phases of the division output and the input clock signal coincide with each other to establish synchronism between them.

Abstract: An impulse response of a litter may change in the output of a filter unit immediately after the generation of a litter according to a sampling timing signal from a timing regenerating unit if a filter unit is provided between an A/D converting unit and an echo canceler. In this case, a selecting unit in a jitter compensating unit compensates an uncanceled echo through each of the outputs sequentially selected by a plurality of adaptive filter unit. Plural sets of tap coefficients are stored in a tap coefficient storage unit, from which the selecting unit sequentially reads them to operate one adaptive filter unit, thereby reducing the size of a jitter compensating circuit.

Abstract: A transversal filter has a transfer function for which a zero point occurs outside a unit circle on z plane and thus the output waveform has a ringing characteristic having a change from negative to positive around a precursor and before a main cursor and is associated and integrated with another transversal filter, thereby forming a waveform shaping decimation filter or a pulse shaping high-pass filter. The waveform decimation filter can eliminate a high frequency noise, changes a high frequency input data to a low frequency output data, and performs a waveform shaping operation. Therefore it cannot require a pulse shaping filter separated from the decimation filter. The pulse shaping high-pass filter includes a pulse shaping filter whose number of the taps is decreased and performs high-pass filter function. A pulse shaping filter whose number of the taps is decreased can be used separately from the high-pass filter.

Abstract: A hybrid circuit includes a two-wire/four-wire conversion unit for forming an interface between a two-wire line and a four-wire line, and a digital balancing unit for canceling a return echo passing through an echo return route including the conversion unit. The digital balancing unit includes first through fourth parts. The first part determines values of elements of a ladder type circuit composed of resistors and capacitors. The ladder type circuit corresponds to an original equivalent circuit having an impedance obtained by viewing the two-wire line from the conversion unit. The second part generates an impedance function of the original equivalent circuit in the form of a z function in accordance with a bilinear transform using an over-sampling frequency. The third part generates filter coefficients of a digital filter by inserting the impedance function into a transfer function of the echo return route.

Abstract: A balancing network of a wave digital type filter including 3-port pair transforming adaptors (21 to 26) connected in cascade each having a capacitor (C) and a resistor (R) as constituent elements and performing a filter operation function. There is no reflected wave from each port pair other than the two port pairs for the cascade connection of the transforming adaptors (22, 24, 26) each including resistor (R), that port pair is eliminated, and adjoining transforming adaptors (21, 23, 25) each including capacitor (C) are combined to form new 3-port pair combined transforming adaptors (41). Thus, it becomes possible to realize a filter operation by a lesser amount of operations than the sum of the amounts of operations by the 3-port pair transforming adaptors (21 to 26).

Abstract: An adaptive echo canceller for suppressing an echo in an input signal by a pseudo echo, includes a pseudo echo generation filter having a predicted impulse response sequence of an echo path as filter coefficients thereof for generating a pseudo echo, a coefficient renewal part for adaptively renewing the filter coefficients of the pseudo echo generation filter, and a part for suppressing an echo by the pseudo echo which is generated by the pseudo echo generation filter. The coefficient renewal part includes a part for dividing renewed filter coefficients into a plurality of groups each having a certain number of renewed filter coefficents, and a part for successively selecting one group with a predetermined period and carrying out a correction process with respect to the renewed filter coefficients within the selected group, where the correction process corrects an accumulation of errors of renewal processes.

Abstract: An adjustable attenuator circuit in which sampled electric charges are partially transferred from a sampling capacitor to a charge dividing capacitor during a short time within each sampling period, and electric charges stored in the charge dividing capacitor are additively transferred to an integrating capacitor or are discharged to ground according to the content of a weighting coefficient which determines the attenuation factor of the adjustable attenuator circuit.