Patents by Inventor Mitsuo Kawashima

Mitsuo Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4620206
    Abstract: A semiconductor device comprises a superlattice semiconductor portion having a plurality of pairs of superlattice semiconductor thin films for forming step differences of band edge energy. The pairs of the thin films are laminated such that parameters which determine the structure of the thin films are monotonically changed in the direction of the lamination of the thin films. Electrodes are disposed to apply an electric field across both ends of the superlattice semiconductor portion. The semiconductor device has a good negative resistance characteristic and a large design freedom of semiconductor device.
    Type: Grant
    Filed: February 9, 1984
    Date of Patent: October 28, 1986
    Assignee: Agency of Industrial Science and Technology
    Inventors: Kimihiro Ohta, Tadashi Nakagawa, Naoyuki Kawai, Takeshi Kojima, Mitsuo Kawashima
  • Patent number: 4236165
    Abstract: Planar semiconductor device including a crystalline layer of Ga.sub.x Al.sub.1-x Sb compound semiconductor (0.1<x<0.3) grown on a GaSB substrate and a narrow energy band gap semiconductor grown as an active layer on the crystalline layer and having electrodes formed on the active layer in the planar form.
    Type: Grant
    Filed: December 5, 1978
    Date of Patent: November 25, 1980
    Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Mitsuo Kawashima, Kimihiro Ohta, Shoei Kataoka
  • Patent number: 4182964
    Abstract: Occurrence of high field domain in the conventional Gunn diode is prevented by covering a solid body such as a semiconductor element partially or wholly by a dielectric member or by a control element such as a metallic layer coupled reactively with the solid body through a dielectric member, whereby a solid state element having a negative differential conductivity is obtained. Such a type of negative-resistance solid state element, together with its various modes of embodimental construction disclosed herein, affords a superior solid state element which is applicable to amplifiers, oscillators, logic memories, and the like of millimeter or submillimeter bands.
    Type: Grant
    Filed: July 20, 1972
    Date of Patent: January 8, 1980
    Assignee: Kogyo Gijutsuin
    Inventors: Shoei Kataoka, Hiroshi Tateno, Hiroyuki Fujisada, Hideo Yamada, Mitsuo Kawashima, Yasuo Komamiya
  • Patent number: 4047199
    Abstract: The invention disclosed relates to a bulk semiconductor device having a semiconductor element exhibiting a negative conductivity under a high electric field and being capable of generating a high electric field domain therein. The semiconductor device includes two ohmic electrodes disposed at opposite ends to apply a bias voltage, at least one means for generating a high electric field domain in the semiconductor device by means applying an input signal to the generating means, at least one means for inhibiting generation of a high electric field domain by means applying another input signal to the inhibiting means, and means for detecting the existence of the high electric field domain in the semiconductor device to produce an output signal.
    Type: Grant
    Filed: October 1, 1975
    Date of Patent: September 6, 1977
    Assignee: Agency of Industrial Science & Technology
    Inventors: Shoei Kataoka, Yasuo Komaniya, Nobuo Hashizume, Kazutaka Tomizawa, Mitsuo Kawashima
  • Patent number: 4021680
    Abstract: Disclosed is a bulk semiconductor device which employs a semiconductor element exhibiting negative conductivity under a high electric field. Said semiconductor element has at least two regions and at least one bridge portion and each region thereof is connected with the region adjacent thereto by a bridge portion. Means for controlling the lateral spatial growth of a high electric field domain is provided on or near each bridge portion. The growth of a high electric field domain generated in one of the regions into the adjacent region is controlled by applying a signal to said controlling means.
    Type: Grant
    Filed: October 1, 1975
    Date of Patent: May 3, 1977
    Assignee: Agency of Industrial Science & Technology
    Inventors: Shoei Kataoka, Yasuo Komamiya, Mitsuo Kawashima, Nobuo Hashizume, Kazutaka Tomizawa