Abstract: A solid-state image sensing device according to the invention which can reduce an instantaneous current occurring in transferring image digital signals from analog-digital converters to registers to reduce noise sneaking into the analog-digital converters and a pixel array includes a pixel array, a vertical scanning circuit, a plurality of column ADCs, a plurality of registers, and control signal generation units. The control signal generation units are provided for respective groups into which the column ADCs and the registers disposed on one side of the pixel array are divided, and generate control signals of different timings, for respective units including at least one group, of transfer of converted image digital signals to the registers from the column ADCs operating in parallel.

Abstract: A solid-state image sensing device according to the invention which can reduce an instantaneous current occurring in transferring image digital signals from analog-digital converters to registers to reduce noise sneaking into the analog-digital converters and a pixel array includes a pixel array, a vertical scanning circuit, a plurality of column ADCs, a plurality of registers, and control signal generation units. The control signal generation units are provided for respective groups into which the column ADCs and the registers disposed on one side of the pixel array are divided, and generate control signals of different timings, for respective units including at least one group, of transfer of converted image digital signals to the registers from the column ADCs operating in parallel.

Abstract: A solid-state image pickup device includes plural pixels, a voltage generator that generates a reference voltage, plural comparators that are aligned in one direction, and compare respective voltages output from the pixels with the reference voltage, a counter that counts in tandem with a change in the reference voltage generated by the voltage generator, plural buffer circuits that are connected in series with the counter, and each sequentially receives an output of the counter; plural latch circuits that take in a value input to an input terminal thereof according to respective trigger signals output from the comparators, a common signal line that is commonly connected to respective inputs of the latch circuits, and plural signal lines that are connected to respective outputs of the buffer circuits, and allow the output of the counter to propagate therethrough.

Abstract: In a solid-state image pickup device, each pixel at a selected row outputs to a corresponding column signal line a first analog signal in accordance with an amount of electric charges at an electric charge accumulation section in an initial state and a second analog signal in accordance with an amount of photoelectric charges transferred to the electric charge accumulation section. An A/D converter provided at each column performs A/D conversion on the first and second analog signals to output first and second digital signals, respectively. Of first to third latch circuits provided at each column, the first latch circuit takes in and holds the first digital signal outputted from the A/D converter. The second latch circuit takes in and holds the first digital signal held at the first latch circuit. The third latch circuit takes in and holds the second digital signal outputted from the A/D converter.

Abstract: In a solid-state image pickup device, each pixel at a selected row outputs to a corresponding column signal line a first analog signal in accordance with an amount of electric charges at an electric charge accumulation section in an initial state and a second analog signal in accordance with an amount of photoelectric charges transferred to the electric charge accumulation section. An A/D converter provided at each column performs A/D conversion on the first and second analog signals to output first and second digital signals, respectively. Of first to third latch circuits provided at each column, the first latch circuit takes in and holds the first digital signal outputted from the A/D converter. The second latch circuit takes in and holds the first digital signal held at the first latch circuit. The third latch circuit takes in and holds the second digital signal outputted from the A/D converter.

Abstract: A solid-state image sensing device according to the invention which can reduce an instantaneous current occurring in transferring image digital signals from analog-digital converters to registers to reduce noise sneaking into the analog-digital converters and a pixel array includes a pixel array, a vertical scanning circuit, a plurality of column ADCs, a plurality of registers, and control signal generation units. The control signal generation units are provided for respective groups into which the column ADCs and the registers disposed on one side of the pixel array are divided, and generate control signals of different timings, for respective units including at least one group, of transfer of converted image digital signals to the registers from the column ADCs operating in parallel.

Abstract: A solid-state image pickup device includes plural pixels, a voltage generator that generates a reference voltage, plural comparators that are aligned in one direction, and compare respective voltages output from the pixels with the reference voltage, a counter that counts in tandem with a change in the reference voltage generated by the voltage generator, plural buffer circuits that are connected in series with the counter, and each sequentially receives an output of the counter; plural latch circuits that take in a value input to an input terminal thereof according to respective trigger signals output from the comparators, a common signal line that is commonly connected to respective inputs of the latch circuits, and plural signal lines that are connected to respective outputs of the buffer circuits, and allow the output of the counter to propagate therethrough.

Abstract: The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

Abstract: The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

Abstract: The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

Abstract: The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

Abstract: An object is to provide a semiconductor integrated circuit capable of controlling the output resistance value of an output buffer circuit always at a given value without deteriorating the data transmission quality. D latches (60-63, 65-68) in latch circuit portions (16, 17) in an output resistance control output buffer circuit (2) receive an output resistance control trigger signal (STRB) in common at their respective T inputs. The D latches (60-63) also receive pull-up bit control signals (U0-U3) at their respective D inputs, and the D latches (65-68) also receive pull-down bit control signals (D0-D3) at their respective D inputs. The output resistance value of transistors (QU0-QU3) and transistors (QD0-QD3) is controlled with the data latched in the latch circuit portions (16, 17), respectively.