Abstract: In a data flow machine, a program stored in advance is read out based on a tag included in a packet when the packet including first data is inputted from an external portion. Then, an instruction packet is formed by the content read out as a new tag and the first data, so that the instruction packet is outputted. Second data including the same tag as that included in the first data of the instruction packet read out from the program memory is detected. Firing processing is performed with respect to the first data and the second data as a pair and arithmetic processing is performed according to the instruction as a part of the tag included in an arithmetic packet, so that the arithmetic packet is outputted as a packet. The tag included in the packet is determined and the packet is outputted to an external portion or is inputted again to the internal portion.

Abstract: In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module, and the daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Abstract: In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module. The daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Abstract: A simulation method and a computer therefor, i.e., a simulator, for simulating operation of a circuit employing logic gates. The simulation method is to be called the event drive method, in which the output processing is executed only when an input to cause output changes and the output level and the start and finish time for the level are sent out. Hence the number of packets of data flowing for simulation can be minimized and also the number of times of data processing is reduced. This system is applied to each component in a logic circuit, whereby the parallel execution of processing as to the parallel components is possible so as to devise the simulation at a higher speed.