Patents by Inventor Mitsuo Natsume

Mitsuo Natsume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100135753
    Abstract: A load port is disclosed which allows a wafer to be transferred between the inside of a FOUP and the inside of a semiconductor fabrication apparatus even during a purge operation. The load port is provided adjacent the semiconductor fabrication apparatus in a clean room and includes a purge stage having a purge port through which a gas atmosphere in the FOUP is replaced into nitrogen gas or dry air, an opener stage provided in a juxtaposed relationship with the purge stage and having an opening communicating with the inside of the semiconductor fabrication apparatus and a door section capable of opening and closing the opening, and a moving mechanism for moving the FOUP between the purge stage and the opener stage.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 3, 2010
    Applicant: SINFONIA TECHNOLOGY CO., LTD.
    Inventors: Mitsuo Natsume, Shin Kawahisa, Takumi Mizokawa
  • Publication number: 20090241302
    Abstract: The carrier base 3 is movably installed at the upper part of the FOUP opener main body 50b, and the clamping base 4 is movably installed at the upper part of the carrier base 3. The clamp lever 5a is rotatably supported by the rotating shaft 5c at the upper part of the clamping base 4, and the clamping pawl 5b is formed on the clamp lever 5a. The carrier base 3 and the FOUP 2 integrally move. The clamping pawl 5b, which is accommodated into the clamping recess 2h, presses the clamped portion 2c from above to below, by which the FOUP 2 is fixed to the mounting base 51.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Applicant: SHINKO ELECTRIC CO., LTD.
    Inventor: Mitsuo Natsume
  • Publication number: 20090142170
    Abstract: A load port particularly well-suited to application in batch processing semiconductor manufacturing processes is provided with a load port main body having a main table onto which a FOUP containing wafers is placed, a mapping means for mapping the wafers contained within the FOUP, and the like, and is further provided with a displacing means for moving the FOUP placed on the main table between the main table and a predetermined position removed a distance from the load port main body, in which the displacing mechanism is provided with an open space enabling the passing of a FOUP which contains wafers between the aforementioned predetermined position and a piece of equipment located adjacent to the load port main body.
    Type: Application
    Filed: November 19, 2008
    Publication date: June 4, 2009
    Applicant: Shinko Electric., Ltd.
    Inventor: Mitsuo Natsume