Abstract: A solid-state imaging apparatus having a plurality of pixels, comprising: a substrate; a wiring layer formed on the substrate and including an insulating film and a plurality of wires; a plurality of lower electrodes formed on the wiring layer in one-to-one correspondence with the plurality of pixels; a photoelectric conversion film formed covering the plurality of lower electrodes; a light-transmissive upper electrode formed on the photoelectric conversion film; and a shield electrode extending through a gap between each pair of adjacent lower electrodes among the plurality of lower electrodes, the shield electrode having a fixed potential and being electrically insulated from the plurality of lower electrodes.

Abstract: A solid-state imaging apparatus having a plurality of pixels, comprising: a substrate; a wiring layer formed on the substrate and including an insulating film and a plurality of wires; a plurality of lower electrodes formed on the wiring layer in one-to-one correspondence with the plurality of pixels; a photoelectric conversion film formed covering the plurality of lower electrodes; a light-transmissive upper electrode formed on the photoelectric conversion film; and a shield electrode extending through a gap between each pair of adjacent lower electrodes among the plurality of lower electrodes, the shield electrode having a fixed potential and being electrically insulated from the plurality of lower electrodes.

Abstract: A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode.

Abstract: A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode.

Abstract: A semiconductor device includes semiconductor elements and at least one dummy pattern. Each or at least some of the semiconductor elements has a Damascene gate structure or a replacing gate structure and is located in element-forming regions. In addition, at least a dummy pattern is located in a region different from the element-forming regions. The dummy pattern may have a semiconductor element structure of the same or different kind from the Damascene gate structure or replacing gate structure. The dummy pattern may be a pattern of an insulating film, an interface transistor, or an analog circuit capacitor electrode instead of the dummy gate.

Abstract: A semiconductor device includes semiconductor elements and at least one dummy pattern. Each or at least some of the semiconductor elements has a Damascene gate structure or a replacing gate structure and is located in element-forming regions. In addition, at least a dummy pattern is located in a region different from the element-forming regions. The dummy pattern may have a semiconductor element structure of the same or different kind from the Damascene gate structure or replacing gate structure. The dummy pattern may be a pattern of an insulating film, an interface transistor, or an analog circuit capacitor electrode instead of the dummy gate.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Mounted on a single semiconductor substrate are a DRAM, MOS transistor, resistor, and capacitor. The gate electrode of the DRAM and the gate electrode of the MOS transistor are formed by a common layer (i.e., a first-level poly-Si layer). The storage electrode of the DRAM. the resistor, and the lower electrode of the capacitor are formed by a common layer (i.e., a third-level poly-Si layer). The plate electrode of the DRAM and the upper electrode of the capacitor are formed by a common layer (i.e., a fourth-level poly-Si layer).

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: A semiconductor memory device includes a capacitor and an insulating separation area in a trench formed around a switching transistor, with a storage electrode of the capacitor being sandwiched between an upper and a lower cell plate electrode to reduce leakage current due to the parasitic MOS transistor effect in the trench sidewall along the channel in the switching transistor and leakage current due to the gate-controlled diode effect in the trench sidewall. Also, a method is disclosed for manufacturing such semiconductor memory device.