Abstract: In a microprocessor capable of carrying out instructions having different data lengths including an instruction decoder, a register, an operational circuit and a control circuit for controlling the register and the operational unit, the register is divided into a plurality of register units, and the operational circuit is divided into a plurality of operational circuits units, each of which is connected to one of the register units. The control circuit selectively operates the register units and the operation circuit units in accordance with outputs of the instruction decoder.

Abstract: An arithmetic and logic operation system capable of performing an arithmetic and logic operation for data longer than one word, includes an arithmetic and logic unit for performing an arithmetic and logic operation for a less significant one-word length portion of the data, and an incrementer/decrementer for incrementing or decrementing of a more significant data portion exceeding the one-word length of the data. A carry signal or a borrow signal generated in the arithmetic and logic unit is supplied to the incrementer/decrementer so that the incrementer/decrementer is controlled so as to selectively increment, or decrement the received data or alternately to output the received data without modification.

Abstract: A graphics device LSI capable of achieving a high speed paint-out processing, including a pattern reproduction part for forming a duplicate pattern PD of a paint-out pattern, a shift number calculation part for calculating a shift number S from a formation position of a paint-out drawing on an image memory, a paint-out pattern length and a word length, and a data extraction part for extracting paint-out data of the word length by shifting the duplicate pattern PD by the shift number S.

Abstract: A memory access control circuit determines an optimum memory access mode and performs the optimum memory access mode without requiring additional data from the data processing unit. The circuit performs a plurality of memory access operations, the number of which is larger than the number of access modes designated by the data processing unit, and decides automatically which memory access is to be performed, and independently executes the appropriate memory access. The memory access control circuit provides memory access control functions which make it particularly suited for use in a graphics display system.

Abstract: A figure filling device fills a figure in memory defined by X-Y coordinate scan line by scan line with reference to a specified pattern. In the filling of a new scan line, the coordinate data for the ends of the new scan line, for the ends of the previously processed scan line and for the reference point of the previous pattern are subjected to a certain processing so that the coordinate data for the reference point of the new pattern is determined. The filling device determines the address in the memory corresponding to the coordinates for the reference point of the new pattern and the address on the memory corresponding to the coordinates for the ends of the new scan line. A filling pattern is read out of the pattern address in the memory and the scan line data is read out of the scan line address on the memory so that they are subjected to a predetermined operation. The result is written to the scan line address.

Abstract: A curve generator has a group of registers, a group of files, an operator, a comparator and a sequencer. The curve generator interpolates for a curve in the vicinity of a plurality of designated control points, for example, a Bezier curve or a Spline curve, by calculating coordinate values of middle points between the control points on the basis of coordinate values of said control points. The curve generator realizes, an exclusive hardware, from an algorithm for generating the curve and, therefore, is capable of generating the curve at extremely high speed.

Abstract: An external synchronism control circuit is triggered in synchronism with an external synchronous signal so as to successively generate addresses to an image memory storing image information. The external synchronism control circuit comprises a synchronism register receiving the external synchronous signal and capable for holding a plurality of set values. When the external synchronous signal is applied, the synchronism register is initialized to be set with an initial value of the plurality of set values. The content of the synchronism register is updated from one set value to another set value when a predetermined period of time has elapsed. When the content of the synchronism register is updated to a final value of the plurality of set values, the synchronism register operates to maintain the final value until a next external synchronous signal is applied.

Abstract: A graphics display controller for transferring figure data to an overlapping portion of a destination area and a drawing-enable area, the drawing-enable area being defined by a clipping rectangle having a diagonal line defined by first and second coordinate data. The controller includes a comparator comparing the coordinate data of each word in the destination area with the first and second coordinate data, a first mask data circuit responding to a comparison result from the comparator to generate first mask data designating bit or bits of each word of the destination area contained in the drawing-enable area, a second mask data circuit responding to a position of the word of the destination area to generate second mask data designating bit or bits of the word containing the destination area, and a drawing control circuit writing the figure data into the bit or bits designated by both of the first and second mask data.

Abstract: An image processing apparatus capable of shrinking or enlarging images. A plurality of bits representing the image to be processed are applied in word format to a plurality of gate circuits which selectively pass certain ones of the bits in each received word in accordance with a selected shrinking or enlargement scale factor. For shrinking the gate circuits pass selected ones of the bits forming each word, but less than the number of bits in a received word. For enlargement the gate circuits pass the full number of bits in each word, but cause the bits constituting a word at the output of the gate circuits to contain two or more bits of the same content as that of at least the first bit of each input word. Packing apparatus is provided to pack bits at the output of the gate circuits representing a shrunk image into words having a number of bits equal to that of input words to the gate circuits.

Abstract: A slave processor adapted to execute a read/write operation in response to a read/write request signal from a master processor, comprises a first circuit for performing a write operation during a predetermined period of time from the moment a first write request signal is made inactive from an active condition. An second circuit is provided for generating, when another access request signal such as a second write request signal or a read request signal is made active during the above predetermined period of time, an active wait signal requiring the master processor to maintain the second access request signal in an active condition. The second circuit also operates to delay an operation indicated by the second access request signal.