Patents by Inventor Mitsuru Shimazu

Mitsuru Shimazu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9647058
    Abstract: A diode having excellent switching characteristics is provided. A diode includes a silicon carbide substrate, a stop layer, a drift layer, a guard ring, a Schottky electrode, an ohmic electrode, and a surface protecting film. At a measurement temperature of 25° C., a product R•Q of a forward ON resistance R of the diode and response charges Q of the diode satisfies relation of R•Q?0.24×Vblocking2. The ON resistance R is found from forward current-voltage characteristics of the diode. A reverse blocking voltage Vblocking is defined as a reverse voltage which produces breakdown of the diode. The response charges Q are found by integrating a capacitance (C) obtained in reverse capacitance-voltage characteristics of the diode in a range from 0 V to Vblocking.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: May 9, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Kiyama, Takashi Matsuura, Mitsuru Shimazu
  • Publication number: 20150221780
    Abstract: A diode having excellent switching characteristics is provided. A diode includes a silicon carbide substrate, a stop layer, a drift layer, a guard ring, a Schottky electrode, an ohmic electrode, and a surface protecting film. At a measurement temperature of 25° C., a product R•Q of a forward ON resistance R of the diode and response charges Q of the diode satisfies relation of R•Q?0.24×Vblocking2. The ON resistance R is found from forward current-voltage characteristics of the diode. A reverse blocking voltage Vblocking is defined as a reverse voltage which produces breakdown of the diode. The response charges Q are found by integrating a capacitance (C) obtained in reverse capacitance-voltage characteristics of the diode in a range from 0 V to Vblocking.
    Type: Application
    Filed: February 4, 2015
    Publication date: August 6, 2015
    Inventors: Makoto KIYAMA, Takashi MATSUURA, Mitsuru SHIMAZU
  • Patent number: 8829535
    Abstract: A silicon carbide semiconductor device includes an insulation film, and a silicon carbide layer having a surface covered with the insulation film. The surface includes a first region. The first region has a first plane orientation at least partially. The first plane orientation is any of a (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsuru Shimazu, Toru Hiyoshi, Keiji Wada, Takeyoshi Masuda
  • Patent number: 8642476
    Abstract: There is provided a method for manufacturing a SiC semiconductor device achieving improved performance. The method for manufacturing the SiC semiconductor device includes the following steps. That is, a SiC semiconductor is prepared which has a first surface having at least a portion into which impurities are implanted. By cleaning the first surface of the SiC semiconductor, a second surface is formed. On the second surface, a Si-containing film is formed. By oxidizing the Si-containing film, an oxide film constituting the SiC semiconductor device is formed.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: February 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Satomi Itoh, Hiromu Shiomi, Yasuo Namikawa, Keiji Wada, Mitsuru Shimazu, Toru Hiyoshi
  • Publication number: 20130341648
    Abstract: A first layer of a first conductivity type made of silicon carbide is formed. A second layer of a second conductivity type different from the first conductivity type positioned on the first layer, and a third layer of the first conductivity type positioned on the second layer are formed. The step of forming second and third layers includes the steps of performing impurity ion implantation, and performing heat treatment for activating impurities implanted by the impurity ion implantation. After the step of performing heat treatment, a trench having a side wall penetrating the third layer and the second layer and having a bottom reaching the first layer is formed. A gate insulating film to cover the side wall of the trench is formed. As a result, a silicon carbide semiconductor device having a low ON resistance is provided.
    Type: Application
    Filed: May 23, 2013
    Publication date: December 26, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yu Saitoh, Takeyoshi Masuda, Sou Tanaka, Kenji Hiratsuka, Mitsuru Shimazu, Kenji Kanbara
  • Publication number: 20120214309
    Abstract: A method of fabricating a SiC semiconductor device includes the steps of preparing a silicon carbide semiconductor including a first surface having impurities implanted at least partially, forming a second surface by dry etching the first surface of the silicon carbide semiconductor using gas including hydrogen gas, and forming an oxide film constituting the silicon carbide semiconductor device on the second surface.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 23, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Satomi Itoh, Hiromu Shiomi, Yasuo Namikawa, Keiji Wada, Mitsuru Shimazu, Toru Hiyoshi
  • Publication number: 20120208302
    Abstract: There is provided a method for manufacturing a SiC semiconductor device achieving improved performance. The method for manufacturing the SiC semiconductor device includes the following steps. That is, a SiC semiconductor is prepared which has a first surface having at least a portion into which impurities are implanted. By cleaning the first surface of the SiC semiconductor, a second surface is formed. On the second surface, a Si-containing film is formed. By oxidizing the Si-containing film, an oxide film constituting the SiC semiconductor device is formed.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 16, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Satomi Itoh, Hiromu Shiomi, Yasuo Namikawa, Keiji Wada, Mitsuru Shimazu, Toru Hiyoshi
  • Patent number: 6387722
    Abstract: The present invention provides an epitaxial wafer comprising a (111) substrate of a semiconductor having cubic crystal structure, a first GaN layer having a thickness of 60 nanometers or more, a second GaN layer having a thickness of 0.1 &mgr;m or more and a method for preparing it.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: May 14, 2002
    Assignee: Sumitomo Electric Industries, LTD
    Inventors: Kensaku Motoki, Masato Matsushima, Katsushi Akita, Mitsuru Shimazu, Kikurou Takemoto, Hisashi Seki, Akinori Koukitu
  • Patent number: 6270587
    Abstract: The present invention provides an epitaxial wafer comprising a (111) substrate of a semiconductor having cubic crystal structure, a first GaN layer having a thickness of 60 nanometers or more, a second GaN layer having a thickness of 0.1 &mgr;m or more and a method for preparing it.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: August 7, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Masato Matsushima, Katsushi Akita, Mitsuru Shimazu, Kikurou Takemoto, Hisashi Seki, Akinori Koukitu
  • Patent number: 6122170
    Abstract: A ceramic base plate of aluminum nitride ceramics, for example, as a power module board has a metal layer on a surface of the ceramic base plate at a fixing portion at which the ceramic base plate is fixed onto a heat radiating plate. Further, a metal film is provided entirely on the rear surface of the ceramic base plate. An IGBT chip or the like is fixed onto the ceramic base plate with a conductive layer interposed therebetween, to form a power module board. Therefore, it is possible to avoid the generation of cracks when the ceramic base plate is mechanically fixed onto the heat radiating plate without using solder, and heat radiation from the ceramic base plate to the heat radiating plate can be improved.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: September 19, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiyuki Hirose, Kazutaka Sasaki, Mitsuru Shimazu, Hirohiko Nakata
  • Patent number: 6031252
    Abstract: An epitaxial wafer enabling epitaxial growth at a high temperature includes a compound semiconductor substrate containing As or P, and a covering layer including GaN; or InN; or AlN; or a nitride mixed-crystalline material containing Al, Ga, In and N. The covering layer covers at least a front surface and a back surface of the substrate. A method of preparing such an epitaxial wafer including steps of growing the covering layer at a growth temperature of at least 300.degree. C. and less than 800.degree. C. so as to cover at least the front and back surfaces of the substrate, and then annealing the substrate having the covering thereon layer at a temperature of at least 700.degree. C. and less than 1200.degree. C.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: February 29, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Miura, Mitsuru Shimazu, Kensaku Motoki, Takuji Okahisa, Masato Matsushima, Hisashi Seki, Akinori Koukitu
  • Patent number: 5970314
    Abstract: A process for forming a high quality epitaxial compound semiconductor layer of indium gallium nitride In.sub.x Ga.sub.1-x N, (where 0<x<1) on a substrate. A first gas including indium trichloride (InCl.sub.3) and a second gas including ammonia (NH.sub.3) are introduced into a reaction chamber and heated at a first temperature. Indium nitride (InN) is grown epitaxially on the substrate by nitrogen (N.sub.2) carrier gas to form an InN buffer layer. Thereafter, a third gas including hydrogen chloride (H1) and gallium (Ga) is introduced with the first and second gases into a chamber heated at a second temperature higher than the first temperature and an epitaxial In.sub.x Ga.sub.1-x N layer is grown on the buffer layer by N.sub.2 gas. By using helium, instead of N.sub.2, as carrier gas, the In.sub.x Ga.sub.1-x N layer with more homogeneous quality is obtained. In addition, the InN buffer layer is allowed to be modified into a GaN buffer layer.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: October 19, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takuji Okahisa, Mitsuru Shimazu, Masato Matsushima, Yoshiki Miura, Kensaku Motoki, Hisashi Seki, Akinori Koukitu
  • Patent number: 5962875
    Abstract: A light emitting device having higher blue luminance is obtained. A gallium nitride compound layer is formed on a GaAs substrate, and thereafter the GaAs substrate is at least partially removed for forming the light emitting device. Due to the removal of the GaAs substrate, the quantity of light absorption is reduced as compared with the case of leaving the overall GaAs substrate. Thus, a light emitting device having high blue luminance is obtained.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: October 5, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Mitsuru Shimazu, Yoshiki Miura
  • Patent number: 5834325
    Abstract: A light emitting device having higher blue luminance is obtained. A gallium nitride compound layer is formed on a GaAs substrate, and thereafter the GaAs substrate is at least partially removed for forming the light emitting device. Due to the removal of the GaAs substrate, the quantity of light absorption is reduced as compared with the case of leaving the overall GaAs substrate. Thus, a light emitting device having high blue luminance is obtained.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: November 10, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Mitsuru Shimazu, Yoshiki Miura