Patents by Inventor Mitsuru Shimizu
Mitsuru Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5336409Abstract: A composite reverse osmosis membrane comprising a thin membrane and a microporous supporting membrane supporting it, wherein said thin membrane mainly comprises a crosslinked polyamide comprising; (a) an amine component containing at least one member selected from the group consisting of substantially monomeric amine compounds each having at least two primary and/or secondary amino groups, and (b) an acid halide component containing at least one member selected from the group consisting of substantially monomeric cyclic acid halide compounds each having at least two acid halide groups and comprising at least two rings.Type: GrantFiled: January 22, 1993Date of Patent: August 9, 1994Assignee: Nitto Denko CorporationInventors: Hisao Hachisuka, Katsuhide Kojima, Yutaka Nakazono, Mitsuru Shimizu, Masahiko Hirose, Yasuo Kihara, Masatoshi Maeda, Hisashi Ikebata, Kenji Matsumoto
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Patent number: 5293334Abstract: A first power source line is formed around a memory area having a memory cell array, column decoder, row decoder and sense amplifier formed therein. The first power source line is applied with a potential which is obtained by lowering a power source voltage supplied from the exterior. A second power source line is formed in the surrounding region of the first power source line. The second power source line is applied with a ground potential. A first peripheral circuit driven by a voltage between the lowered potential and the ground potential is disposed in an area between the first and second power source lines. The first peripheral circuit is a circuit used for the memory area. A third power source line is formed in the surrounding region of the second power source line. The third power source line is applied with a power source potential supplied from the exterior.Type: GrantFiled: November 27, 1991Date of Patent: March 8, 1994Assignee: Kabushiki Kaisha TobshibaInventor: Mitsuru Shimizu
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Patent number: 5142492Abstract: A semiconductor memory device is disclosed which comprises a regular row/column memory cell array having blocks obtained by dividing the memory cell array in the column and row directions, a first peripheral circuit irregularly provided between the blocks divided in the column direction, a second peripheral circuit provided between the blocks divided in the row direction and including a first decoder, a third peripheral circuit provided between the first peripheral circuit and the respective block and including a second decoder, and a fourth peripheral circuit provided at the marginal portion of the memory cell array and including bonding pads and input protection circuit.Type: GrantFiled: October 2, 1990Date of Patent: August 25, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Shimizu, Syuso Fujii
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Patent number: 5119337Abstract: A semiconductor memory device such as dynamic random access memories comprises a work line drive circuit provided with two MOS transistors and a word line to which a word line drive signal is supplied, a substrate bias generation circuit for applying a bias voltage to a semiconductor substrate for MOS transistors, a burn-in mode detection circuit for detecting a burn-in test mode signal, and a substrate bias control circuit for controlling the substrate bias generation circuit. When the semiconductor memory device is subjected to a burn-in test, the power supply level Vcc is increased to raise the voltage of the word line drive signal as compared to that at a normal operation. Accordingly, a high level word line drive signal will be applied to cell transistors, thereby performing correct screening thereof.Type: GrantFiled: April 16, 1990Date of Patent: June 2, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Shimizu, Syuso Fujii, Shozo Saito
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Patent number: 5073243Abstract: An optical recording medium is made by sputtering a polymeric material in an evacuated chamber to form an under layer on a substrate having a preformed grooved pattern of prepits and pregrooves, and then forming a recording layer on the underlayer in the chamber continuously after forming the underlayer. Said under layer is made of a high polymeric material which can be melted, sublimated, or decomposed at a lower temperature than the melting point, the sublimating point, or the decomposing temperature of said recording layer. Accordingly, said under layer can relax the thermal shock transferred from said substrate into said recording layer, and the deformation of said substrate can be prevented, even though a laser beam for playback is repeatedly radiated onto said recording layer, and said optical recording medium has a larger recording sensitivity than the recording sensitivity of an optical recording disc of a prior art.Type: GrantFiled: December 29, 1989Date of Patent: December 17, 1991Assignees: Hitachi Maxwell, Ltd, Hitachi, LtdInventors: Akira Gotoh, Yukinobu Yamazaki, Naoyuki Kikuchi, Shinkichi Horigome, Motoyasu Terao, Horoyuki Suzuki, Makoto Kitoh, Yuichi Kokaku, Mitsuru Shimizu
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Patent number: 5072271Abstract: A protection circuit is inserted between a signal input pad and an internal circuit. The protection circuit includes a parasitic bipolar transistor which is obtained by forming high-impurity concentration semiconductor regions in the major-surface region of a substrate. In practice, it is hard to provide a parasitic bipolar transistor of a sufficiently large size, since the reduction of the size of a chip is a recent trend. With this in mind, a third semiconductor region serving as an electron-trapping region is formed in a region outside of the location where the parasitic bipolar transistor is formed. If an excessive voltage produced by ESD or the like is applied to the pad, and the excessive voltage uncontrollable by the parasitic bipolar transistor, the third semiconductor region absorbs the excessive voltage. In particular, where the current capacity of the parasitic bipolar transistor is small, the third semiconductor region reliably prevents electrostatic destruction of a circuit element.Type: GrantFiled: August 6, 1990Date of Patent: December 10, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Shimizu, Yoshio Okada, Kiyofumi Sakurai
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Patent number: 5066997Abstract: A semiconductor device comprises a semiconductor chip and a memory array constituted by a plurality of memory blocks formed in the semiconductor chip and each having the essentially same construction and a plurality of bit lines arranged in columns at a predetermined interval. The semiconductor device further comprises a dummy wiring pattern arranged ajacent to the memory array in the semiconductor chip and including a dummy wiring layer set apart from outermost bit lines of each memory block a distance equal to the predetermined interval.Type: GrantFiled: November 15, 1989Date of Patent: November 19, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Kiyofumi Sakurai, Syuso Fujii, Mitsuru Shimizu
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Patent number: 4994874Abstract: First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad.Type: GrantFiled: October 24, 1989Date of Patent: February 19, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Shimizu, Yoshio Okada, Syuso Fujii, Shozo Saito
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Patent number: 4962320Abstract: An input protection circuit for MOS devices includes a first resistor and a first parasitic bipolar transistor connected between an input pad and an input buffer circuit of a MOS device. The input protection circuit for MOS devices further includes a second resistor and a second parasitic bipolar transistor connected at a preceding stage of the input buffer circuit so that the gate oxide film of the input buffer circuit can be protected from being damaged by static charges or a voltage which is accidentally generated, without increasing the pattern size of the first parasitic bipolar transistor.Type: GrantFiled: July 13, 1989Date of Patent: October 9, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Okada, Sadao Imada, Mitsuru Shimizu
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Patent number: 4908250Abstract: In an optical recording medium, an under layer is formed between an even pattern of a substrate and a recording layer, and said under layer is made of a high polymeric material which can be melted, sublimated, or decomposed at a lower temperature than the melting point, the sublimating point, or the decomposing temperature of said recording layer. Accordingly, said under layer can relax the thermal shock transferred from said substrate into said recording layer, and the deformation of said substrate can be prevented, even through a laser beam for playback is repeatedly radiated onto said recording layer, and said optical recording medium has a larger recording sensitivity than the recording sensitivity of an optical recording disc of a prior art.Type: GrantFiled: September 19, 1988Date of Patent: March 13, 1990Assignees: Hitachi Maxell, Ltd., Hitachi, Ltd.Inventors: Akira Gotoh, Yukinobu Yamazaki, Naoyuki Kikuchi, Shinkichi Horigome, Motoyasu Terao, Hiroyuki Suzuki, Makoto Kitoh, Yuichi Kokaku, Mitsuru Shimizu
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Patent number: 4896294Abstract: A memory cell contains a first MOS transistor, a second MOS transistor, and a capacitor, which are connected at the first ends to one another. A word line for a first cell series, is connected to the gates of first MOS transistors in the memory cells arrayed in a row. A word line for a second cell series, is connected to the gates of second MOS transistors arrayed in a column. A bit line for the first cell series, is connected to the second ends of the first MOS transistors in the row. A bit line for the second cell series, is connected to the second ends of the second MOS transistors in the column. A selection circuit selects the first cell series or the second cell series, according to an external input signal for cell series selection. According to the semiconductor memory deivce, one of the first and second cell array series of the memory cell array can be accessed according to a logic level of the array series select signal.Type: GrantFiled: October 25, 1988Date of Patent: January 23, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Shimizu, Nobuyuki Ikumi
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Patent number: 4876133Abstract: A transparent substrate and a method of producing the same suitable especially for an optical system for an optical data recording medium using a linearly polarized light as a data reading light such as a magneto-optical recording medium drive unit and an optical data recording medium for reading data using a linearly polarized light.Type: GrantFiled: November 12, 1987Date of Patent: October 24, 1989Assignee: Hitachi Maxell, Ltd.Inventors: Toshinori Sugiyama, Tetsurou Ikegaki, Mitsuru Shimizu, Yoshitane Tuburaya
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Patent number: 4720826Abstract: An optical recording disc comprising two disc substrates, each in a cylindrical shape having a round center hole, at least one recording layer formed on the surface of at least one said disc substrate, and at least one bonding material layer is formed at an inner rim portion and an outer rim portion of the surface of the said disc substrate, on the surface of which the recording layer is formed, except for at least one portion of the said rim portion of the surface of the disc substrate, wherein the bonding material layer is provided to bond the said two disc substrates togehter, so that the surfaces of the said disc substrates, on the surface of which the recording layer is formed, face each other, thereby a space gap is formed between the said disc substrates, and the said one portion of the said rim portion of the surface of the disc substrate, where the bonding material layer is not formed, can act as a ventilation path, through which the air can pass from the said air gap into the outside of the opticalType: GrantFiled: March 18, 1986Date of Patent: January 19, 1988Assignee: Hitachi Maxell, Ltd.Inventors: Toshinori Sugiyama, Mitsuru Shimizu
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Patent number: 4710913Abstract: An optical recording disc comprises a first bonding recess formed near an outside surface of an optical recording disc in a bonding boundary portion between a cylindrical hub and a transparent disc substrate, a disc member bonded with said transparent disc substrate through said cylindrical hub, and a second bonding recess formed near the outside surface of said optical recording disc in a bonding boundary portion between said cylindrical hub and said disc member. Accordingly, said optical recording disc can prevent remainder of a bonding material for bonding a pair of said transparent disc substrates or said transparent disc substrate and said disc member together from pushing out of the outside surface of the optical recording disc, resulting in that focusing for reading and writing an information signal can be properly performed.Type: GrantFiled: June 24, 1986Date of Patent: December 1, 1987Assignee: Hitachi Maxell, Ltd.Inventors: Seiichi Matsushima, Toshio Higashihara, Mitsuru Shimizu, Ken Yoshizawa, Masahiro Suzuki, Toshinori Sugiyama
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Patent number: 4663584Abstract: Two intermediate potentials of small current driving capacity are generated using load elements and MOS transistors, and are respectively supplied to the gates of two MOS transistors which are series-connected between power sources and have large current driving capacity, thus obtaining an intermediate potential from a node between the MOS transistors. The MOS transistors at the output stage are complementarily operated so as not to be turned on at the same time.Type: GrantFiled: May 30, 1986Date of Patent: May 5, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Okada, Mitsuru Shimizu
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Patent number: 4226933Abstract: A method of manufacturing a decorative panel having an embossed surface and different degrees of glass corresponding to a pattern, thereby producing a stereoscopic aspect, i.e., the impression of relief and solidity.Type: GrantFiled: November 28, 1978Date of Patent: October 7, 1980Assignee: Toppan Printing Co., Ltd.Inventors: Hideo Ishizawa, Akira Niwayama, Mitsuru Shimizu, Takashi Kagami