Abstract: An apparatus for driving a liquid jet head comprises: a piezoelectric element which mechanically deforms responsive to an electric signal; a pressure chamber whose volume varies due to the deformation of such element; a discharge port communicated with such chamber; 1st and 2nd charging circuits to charge such element at the same polarity; a discharging circuit to discharge such element; and a control unit for making the 1st charging circuit operative prior to the operation of the 2nd charging circuit. A charge time constant of the 1st charging circuit is set to be sufficiently long that no droplet is emitted. A charge time constant of the 2nd charging circuit is set to be shorter to emit a droplet from the discharge port. The surface tension of the meniscus and the contractive force due to the contraction of the pressure chamber act multiplicatively, so that it is possible to record a droplet of a small dot diameter.

Abstract: An image recording apparatus comprises ink jet recording heads; a carriage for moving and scanning those ink jet heads; and a data recording unit for recording character data such as the date and the like in a blank portion other than a image recording region of the recording medium by use of the ink jet heads which are in this blank portion while the carriage is scanning. The character data is recorded (generally in black) by at least the one ink jet head which is arranged at the endmost portion in the direction of arrangement of the ink jet heads. Since the character data can be recorded in the blank portion while the image is being recorded in the image recording region, the total recording time can be reduced.

Abstract: A hydrocyclone separator for liquid suspensions, particularly useful for the separation of highly concentrated slurries, the separator being provided with a forced discharge means in the form of a screw conveyor extending axially through the underflow discharge end of the hydrocyclone for forcibly discharging highly concentrated underflow fractions which would otherwise tend to stagnate in the underflow nozzle to cause choking thereof. An air column is maintained in the hydrocyclone by feeding air thereinto through the rotational axis of the screw conveyor which is driven by a variable speed motor, controlling rotational speed of the conveyor drive axis and the inspiratory air pressure according to the conditions of the feed slurry.

Abstract: A direct memory access control (DMAC) system, in a data processing system, includes at least a central processing unit and a memory, the memory being capable of storing and providing data in any one of several predetermined formats. A plurality of input/output control ports, each connecting a respective input/output device to a common data bus, control data transfer in either direction between the device and the memory. A direct memory access control unit is connected to the common data bus for receiving an access request signal from any of the plurality of input/output control ports, and is connected to the memory for providing thereto, in response to the access request signal, instructions at least as to the size and desired format of the data transfer. A bus switching unit connects the common data bus to the memory, and is connected to the direct memory access control unit for receiving the instructions.

Abstract: In a multiprocessor system having a plurality of processors, each of identical construction, each processor is internally equipped with a fixed address supply source which generates a non-unique fixed address for accessing a common memory unit over commonly connected bus lines, and a sequential state indicate signal generator for generating a logic "1" or "0" synchronizing signal when a special condition (for example, interrupt) occurs with respect to the processor.A shared memory access control system for a multiprocessor system, as above described, includes circuitry, external to and associated with at least each processor except for one processor, responsive to the synchronizing signal from its respective processor for modifying the non-unique fixed address from the respective processor so that, as a result, each processor is able to address the common memory over the commonly connected bus lines with a unique fixed address.