Patents by Inventor Mitsusada Shibasaka

Mitsusada Shibasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5331397
    Abstract: An inner lead bonding inspecting method comprises the steps of: irradiating an illumination light onto the planar surface of a bonding portion between an electrode bump provided on a semiconductor pellet and an inner lead, measuring the quantity of reflected light from the surface, and judging whether the bonding state of the inner lead bonding is good or bad on the basis of the measured result. According to another aspect, an inner lead bonding inspecting apparatus comprises any irradiation device for irradiating a light onto a planar surface of a bonding portion between an electrode bump provided on a semiconductor pellet and an inner lead; a light quantity measurement device for measuring the quantity of reflected light from the inner lead surface, and a judging device for comparing the measured quantity of reflected light with a reference light quantity, to judge the quality of the bonding state.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: July 19, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Yamanaka, Mitsusada Shibasaka
  • Patent number: 5156319
    Abstract: Wire bonding inspection equipment includes a judging unit for judging whether or not wire bonding of a semiconductor device is acceptabe and for producing a defect signal when the semiconductor device is judged to be defective. In response to the defect signal wires of the defective semiconductor device are broken by a breaking unit, and a defect mark is applied on the defective semiconductor device by a defective mark putting unit in response to the defect signal, the defect mark applying unit applying the defect mark on an area other than an area to be covered with sealing material.
    Type: Grant
    Filed: September 12, 1991
    Date of Patent: October 20, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsusada Shibasaka, Yuichi Miyahara
  • Patent number: 4864514
    Abstract: Wire-bonding of a semiconductor device designed in accordance with the CAD system is implemented on the basis of bonding data obtained by making use of the design data in the CAD system For the design data in the CAD system, coordinate data of the bonding pads and the lead frames and wiring information therebetween are used. Since ordinarily the coordinate system in the CAD system and the coordinate system in the wire-bonding apparatus are not equal to each other, coordinate transformation is applied to the bonding data obtained from the CAD system. The data thus transformed is delivered to the bonding unit. Since there is employed a scheme to utilize the design data in the CAD system, the necessity of inputting bonding data by an operator is eliminated, thus making it possible to carry out bonding work free from an error in a short time.
    Type: Grant
    Filed: August 31, 1987
    Date of Patent: September 5, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Yamanaka, Mitsusada Shibasaka