Patents by Inventor Mitsutoshi Fujita

Mitsutoshi Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8085012
    Abstract: In a sensor driving/measuring system, specifications required by a sensor which requires a high applied voltage are implemented with const increase suppressed. A semiconductor integrated circuit for use in a sensor driving/measuring system driven by a battery includes: a sensor driver for outputting a given voltage to be applied to a sensor; a measuring circuit for receiving and measuring a voltage obtained, through current-voltage conversion, from a current generated in the sensor; and a booster. The booster boosts a given pre-boost voltage to obtain a boosted voltage and supplies the boosted voltage as a power supply voltage to the sensor driver and the measuring circuit.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: December 27, 2011
    Assignee: Panasonic Corporation
    Inventor: Mitsutoshi Fujita
  • Patent number: 7791519
    Abstract: In a pass/fail judgment test for a semiconductor IC having plural DACs, there is a problem that the test time is undesirably increased due to an increase on the number of DACs or an increase in resolution. When testing two DACs, i.e., DAC1 and DAC2, a control unit (170) alternately increases the digital input values of the DAC1 and DAC2, whereby the output of a comparator 1 to which the analog output values of the DAC1 and DAC2 are inputted repeats inversion between “0” and “1”. It is judged whether the DACs are conforming or not by judging with a judgment unit (180) whether the output pattern of the comparator 1 matches an expected value or not.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: September 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuo Matsukawa, Mitsutoshi Fujita
  • Publication number: 20090128382
    Abstract: In a pass/fail judgment test for a semiconductor IC having plural DACs, there is a problem that the test time is undesirably increased due to an increase on the number of DACs or an increase in resolution. When testing two DACs, i.e., DAC1 and DAC2, a control unit (170) alternately increases the digital input values of the DAC1 and DAC2, whereby the output of a comparator 1 to which the analog output values of the DAC1 and DAC2 are inputted repeats inversion between “0” and “1”. It is judged whether the DACs are conforming or not by judging with a judgment unit (180) whether the output pattern of the comparator 1 matches an expected value or not.
    Type: Application
    Filed: March 22, 2007
    Publication date: May 21, 2009
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuo Matsukawa, Mitsutoshi Fujita
  • Publication number: 20090021226
    Abstract: In a sensor driving/measuring system, specifications required by a sensor which requires a high applied voltage are implemented with const increase suppressed. A semiconductor integrated circuit for use in a sensor driving/measuring system driven by a battery includes: a sensor driver for outputting a given voltage to be applied to a sensor; a measuring circuit for receiving and measuring a voltage obtained, through current-voltage conversion, from a current generated in the sensor; and a booster. The booster boosts a given pre-boost voltage to obtain a boosted voltage and supplies the boosted voltage as a power supply voltage to the sensor driver and the measuring circuit.
    Type: Application
    Filed: June 5, 2008
    Publication date: January 22, 2009
    Inventor: Mitsutoshi Fujita
  • Patent number: 7281113
    Abstract: A microcomputer comprises a CPU; a nonvolatile memory; a plurality of volatile memories; a system bus; a program transfer bus; a program transfer section; an address conversion section; and a voltage detection section. The volatile memories include a plurality of memories switchable to be used as transfer and execution memories in accordance with a program execution state by the CPU. Where the voltage detected by the voltage detection section is lower than a first voltage, the program transfer section transfers the part of the program stored in the nonvolatile memory to the transfer memory, and the address conversion section converts an address in the nonvolatile memory output from the CPU into an address in the execution memory.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: October 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsutoshi Fujita, Kenji Tsutsumi
  • Patent number: 7148135
    Abstract: A branching point on a wire is detected in the layout results S101. A delay amount of a route with a dummy buffer being inserted on a wire subsequent to the branching point S102 and that of the route without a dummy buffer being inserted are then calculated S103. Based on the delay amounts, an insertion point at which a load-dividing buffer is to be inserted is determined S104. On condition that a load-dividing buffer is to be inserted at the insertion point, the drive capability of a driving cell preceding the insertion point is calculated so that timing constraints are satisfied S105. Then, after it is confirmed that a load-dividing buffer is insertable at the determined insertion point S106, processes of placing a load-dividing buffer, changing the drive capability of the driving cell, and changing wiring information are performed on the layout results S107.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: December 12, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsutoshi Fujita, Shuji Kondo
  • Publication number: 20050268069
    Abstract: A microcomputer comprises a CPU; a nonvolatile memory; a plurality of volatile memories; a system bus; a program transfer bus; a program transfer section; an address conversion section; and a voltage detection section. The volatile memories include a plurality of memories switchable to be used as transfer and execution memories in accordance with a program execution state by the CPU. Where the voltage detected by the voltage detection section is lower than a first voltage, the program transfer section transfers the part of the program stored in the nonvolatile memory to the transfer memory, and the address conversion section converts an address in the nonvolatile memory output from the CPU into an address in the execution memory.
    Type: Application
    Filed: June 1, 2005
    Publication date: December 1, 2005
    Inventors: Mitsutoshi Fujita, Kenji Tsutsumi
  • Publication number: 20040216069
    Abstract: A branching point on a wire is detected in the layout results S101. A delay amount of a route with a dummy buffer being inserted on a wire subsequent to the branching point S102 and that of the route without a dummy buffer being inserted are then calculated S103. Based on the delay amounts, an insertion point at which a load-dividing buffer is to be inserted is determined S104. On condition that a load-dividing buffer is to be inserted at the insertion point, the drive capability of a driving cell preceding the insertion point is calculated so that timing constraints are satisfied S105. Then, after it is confirmed that a load-dividing buffer is insertable at the determined insertion point S106, processes of placing a load-dividing buffer, changing the drive capability of the driving cell, and changing wiring information are performed on the layout results S107.
    Type: Application
    Filed: April 2, 2004
    Publication date: October 28, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Mitsutoshi Fujita, Shuji Kondo