Patents by Inventor Mitsutoshi Sugawara

Mitsutoshi Sugawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4885581
    Abstract: For reduction in component elements, there is disclosed a digital-to-analog converter circuit for converting a digital input signal consisting of high-order bits and low-order bits into an analog output signal, comprising, (a) a first digital-to-analog converting circuit operative to produce a first current the amount of which corresponds to a value represented by the high-order bits, (b) a memory circuit storing an error data information in each address specified by each of values represented by the high-order bits, (c) an arithmetic circuit operative to carry out arithmetic operations on the low-order bits and the error data information to produce amended low-order bits, (d) a second digital-to-analog converting circuit operative to produce a second current the amount of which corresponds to a value represented by the amended low-order bits, and (e) an analog adder operative to add the first current weighted by a predetermined factor to the second current to produce an analog output signal, so that the anal
    Type: Grant
    Filed: February 26, 1988
    Date of Patent: December 5, 1989
    Assignee: NEC Corporation
    Inventors: Mitsutoshi Sugawara, Nami Inamasu
  • Patent number: 4841177
    Abstract: An improved comparator circuit which can operate stably against noise or fluctuation in a power supply is disclosed. The comparator circuit includes a differential amplifier having first and second input terminal, a first diode for biasing the first input terminal at a constant voltage, a second diode coupled between the first and second input terminals, and means for gradually changing the potential at the first input terminal towards the above constant voltage.
    Type: Grant
    Filed: January 6, 1988
    Date of Patent: June 20, 1989
    Assignee: NEC Corporation
    Inventors: Takahiro Sugiyama, Mitsutoshi Sugawara
  • Patent number: 4694204
    Abstract: A transistor circuit for a signal multiplier used in, for example, a demodulator by means of the Costas loop method is disclosed. The transistor circuit comprises first to third circuit stages each including first and second transistors coupled in a differential form. The first to third circuit stages are connected in tandem with one another such that the output signal current of each circuit stage is supplied to the succeeding circuit stage without a substantial change. Further, each of the first to third circuit stages is supplied with one of or both of two input signals P and Q. As a result, the transistor circuit produces an output signal representing a signal multiplication: P.times.Q.times.(P+Q).times.(P-Q).
    Type: Grant
    Filed: February 28, 1985
    Date of Patent: September 15, 1987
    Assignee: NEC Corporation
    Inventors: Kazunori Nishijima, Mitsutoshi Sugawara
  • Patent number: 4562412
    Abstract: An oscillation circuit has a free-running oscillator operating at a predetermined frequency. A signal generator generates a trigger signal in synchronism with an input signal. The trigger signal is supplied to the free-running oscillator to bring the signal level in the oscillator to a reference level. The oscillator keeps its frequency even when there is no input signal, the frequency being approximately equal to an integer multiplied by the frequency of the input signal.
    Type: Grant
    Filed: May 31, 1983
    Date of Patent: December 31, 1985
    Assignee: NEC Corporation
    Inventors: Mitsutoshi Sugawara, Kazuo Tokuda, Tokio Sawataishi
  • Patent number: 4486718
    Abstract: The present invention provides an amplifier having cascade-connected first and second transistors, a constant current source for supplying an operating current to the first transistor, and a load resistor connected to the collector of the first transistor at one end and to a substantially constant voltage terminal at the other end. The amplifier arrangement of the invention removes the necessity of a large capacitance capacitor for noise suppression.
    Type: Grant
    Filed: March 19, 1982
    Date of Patent: December 4, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Mitsutoshi Sugawara
  • Patent number: 4472646
    Abstract: This invention provides a flip-flop drawing low current and occupying a small area in a semiconductor integrated circuit. The flip-flop has a first and a second transistor having their emitters grounded via a first and a second diode, respectively. The collector of the first transistor is coupled with the base of the second transistor via a third diode. Likewise, the collector of the second transistor is coupled with the base of the first transistor via a fourth diode. The output is derived from the collector of a third transistor having its base-emitter path connected in parallel with the first or second diode to form a current mirror circuit.
    Type: Grant
    Filed: January 15, 1982
    Date of Patent: September 18, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Mitsutoshi Sugawara
  • Patent number: 4119919
    Abstract: A frequency discriminator circuit suitable for fabrication in a semiconductor integrated circuit has an input terminal connected to an input amplifier for producing two signals of opposite phase which are, respectively, applied to the base electrodes of two common-collector connected transistors. One of the two signals is also applied through a phase shifter to the emitters of both transistors. An output differential amplifier has its inputs connected, respectively, to the emitters of the two transistors to produce a frequency-discriminated output signal.
    Type: Grant
    Filed: October 25, 1977
    Date of Patent: October 10, 1978
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Mitsutoshi Sugawara