Patents by Inventor Mitsuyoshi Miyazono
Mitsuyoshi Miyazono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200049762Abstract: In a probe apparatus for performing an electrical measurement by bringing a probe into contact with an inspection target substrate, a transfer table is provided with a needle mark transfer member to which a needle mark of the probe is transferred by a contact with the probe. The needle mark transfer member includes a polyimide resin. A movement mechanism is able to move the needle mark transfer member provided on the transfer table to a contact position where the needle mark transfer member is brought into contact with the probe.Type: ApplicationFiled: August 6, 2019Publication date: February 13, 2020Inventors: Tomohiro Ota, Mitsuyoshi Miyazono, Shinya Koizumi, Atsushi Ishii, Takashi Tasaki
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Patent number: 10082524Abstract: A prober in which a probe head can be easily replaced is provided. A prober 10 includes a main body 12; a stage 11 provided within the main body 12 and configured to place a wafer W thereon; a card 16 provided within the main body 12 to face the stage 11; and a probe head holder 24 provided within the main body 12 and configured to be moved toward the card 16. The card 16 includes a probe head 30 which is detachably attached to the card 16 and has a multiple number of probe needles 35, and the probe head holder 24 is moved toward the card 16 while holding the probe head 30 thereon.Type: GrantFiled: June 6, 2014Date of Patent: September 25, 2018Assignee: TOKYO ELECTRON LIMITEDInventor: Mitsuyoshi Miyazono
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Publication number: 20160161527Abstract: A prober in which a probe head can be easily replaced is provided. A prober 10 includes a main body 12; a stage 11 provided within the main body 12 and configured to place a wafer W thereon; a probe card 16 provided within the main body 12 to face the stage 11; and a probe head holder 24 provided within the main body 12 and configured to be moved toward the probe card 16. The probe card 16 includes a probe head 30 which is detachably attached to the probe card 16 and has a multiple number of probe needles 35, and the probe head holder 24 is moved toward the probe card 16 while holding the probe head 30 thereon.Type: ApplicationFiled: June 6, 2014Publication date: June 9, 2016Inventor: Mitsuyoshi Miyazono
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Patent number: 9194906Abstract: A probe apparatus is provided, comprising a card clamp mechanism configured to detachably clamp a probe card equipped with a plurality of probes; a wafer chuck configured to mount a semiconductor wafer thereon and configured to provide contact between electrodes formed in the semiconductor wafer with the probes of the probe card clamped by the card clamp mechanism with an operation of a drive mechanism; and a card movement mechanism configured to move the card clamp mechanism and the probe card clamped by the card clamp mechanism to at least two positions spaced at a predetermined distance.Type: GrantFiled: March 18, 2013Date of Patent: November 24, 2015Assignee: TOKYO ELECTRON LIMITEDInventor: Mitsuyoshi Miyazono
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Publication number: 20130249581Abstract: A probe apparatus is provided, comprising a card clamp mechanism configured to detachably clamp a probe card equipped with a plurality of probes; a wafer chuck configured to mount a semiconductor wafer thereon and configured to provide contact between electrodes formed in the semiconductor wafer with the probes of the probe card clamped by the card clamp mechanism with an operation of a drive mechanism; and a card movement mechanism configured to move the card clamp mechanism and the probe card clamped by the card clamp mechanism to at least two positions spaced at a predetermined distance.Type: ApplicationFiled: March 18, 2013Publication date: September 26, 2013Applicant: TOKYO ELECTRON LIMITEDInventor: Mitsuyoshi MIYAZONO
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Patent number: 8471585Abstract: A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.Type: GrantFiled: July 21, 2010Date of Patent: June 25, 2013Assignees: Tokyo Electron Limited, Fuji Electric Systems Co., Ltd.Inventors: Mitsuyoshi Miyazono, Shigekazu Komatsu, Dai Shinozaki, Masahiro Kato, Atsushi Yoshida
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Patent number: 8159245Abstract: Installed in a probe device is a holding member for inspection which can be mounted on a chuck. The holding member for inspection includes a support plate capable of mounting thereon a chip in which the power device is formed; pins for positioning the chip mounted on the support plate; and a metal film formed on a surface of the support plate in a range from a mounting area on which the chip is mounted to an exposed area on which the chip is not mounted. When inspecting the power device, the chip is fixed onto the mounting area in the holding member for inspection, one probe pin is brought into contact with a terminal on a top surface of the chip; and another probe pin is brought into contact with the metal film in the exposed area.Type: GrantFiled: October 17, 2007Date of Patent: April 17, 2012Assignee: Tokyo Electron LimitedInventors: Shigekazu Komatsu, Mitsuyoshi Miyazono, Kazuya Asaoka
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Publication number: 20110050269Abstract: A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.Type: ApplicationFiled: July 21, 2010Publication date: March 3, 2011Applicants: TOKYO ELECTRON LIMITED, FUJI ELECTRIC SYSTEMS CO., LTD.Inventors: Mitsuyoshi Miyazono, Shigekazu Komatsu, Dai Shinozaki, Masahiro Kato, Atsushi Yoshida
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Publication number: 20100033199Abstract: Installed in a probe device is a holding member for inspection which can be mounted on a chuck. The holding member for inspection includes a support plate capable of mounting thereon a chip in which the power device is formed; pins for positioning the chip mounted on the support plate; and a metal film formed on a surface of the support plate in a range from a mounting area on which the chip is mounted to an exposed area on which the chip is not mounted. When inspecting the power device, the chip is fixed onto the mounting area in the holding member for inspection, one probe pin is brought into contact with a terminal on a top surface of the chip; and another probe pin is brought into contact with the metal film in the exposed area.Type: ApplicationFiled: October 17, 2007Publication date: February 11, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Shigekazu Komatsu, Mitsuyoshi Miyazono, Kazuya Asaoka