Patents by Inventor Miwako Akiyama
Miwako Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9105716Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the sType: GrantFiled: November 11, 2010Date of Patent: August 11, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Patent number: 8410546Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.Type: GrantFiled: March 20, 2009Date of Patent: April 2, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kawaguchi, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase
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Patent number: 8169023Abstract: An impurity concentration profile in a vertical direction of a p type base contact layer of a power semiconductor device has a two-stage configuration. In other word, the impurity concentration profile is highest at an upper face of the p type base contact layer, has a local minimum value at a position other than the upper face and a lower face of the base contact layer, and has a local maximum value at a position lower than the position of the local minimum value.Type: GrantFiled: July 14, 2009Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Publication number: 20120086073Abstract: A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant.Type: ApplicationFiled: December 15, 2011Publication date: April 12, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Patent number: 8106454Abstract: A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant.Type: GrantFiled: November 6, 2008Date of Patent: January 31, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Patent number: 8049270Abstract: This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.Type: GrantFiled: October 25, 2007Date of Patent: November 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Akio Nakagawa, Yusuke Kawaguchi, Syotaro Ono, Yoshihiro Yamaguchi
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Patent number: 7927952Abstract: A method of manufacturing semiconductor devices comprises forming an semiconductor layer of the first conduction type on a substrate of the first conduction type; forming an anti-oxidizing layer on the surface of the semiconductor layer of the first conduction type, the anti-oxidizing layer having an aperture only through a region for use in formation of a guard ring layer of the second conduction type; forming the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type through implantation of ions into a surface where said anti-oxidizing layer is formed; forming an oxide layer at least in the aperture; forming a base layer of the second conduction type adjacent to the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type; and forming a diffused layer of the first conduction type through implantation of ions into the base layer of the second conduction type.Type: GrantFiled: May 28, 2008Date of Patent: April 19, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Patent number: 7919811Abstract: A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate electrode buried in the trench via the gate insulating film, and a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region.Type: GrantFiled: May 16, 2008Date of Patent: April 5, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Patent number: 7910984Abstract: A semiconductor device includes: a semiconductor substrate; a lateral MOSFET formed in an upper portion of a first region of the semiconductor substrate; a vertical MOSFET formed in a second region of the semiconductor substrate; a backside electrode formed on a lower surface of the semiconductor substrate and connected to a lower region of source/drain regions of the vertical MOSFET; and a connecting member penetrating the semiconductor substrate and connecting one of source/drain regions of the lateral MOSFET to the backside electrode.Type: GrantFiled: January 16, 2009Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Yamaguchi, Yusuke Kawaguchi, Miwako Akiyama
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Publication number: 20110059586Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the sType: ApplicationFiled: November 11, 2010Publication date: March 10, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Miwako AKIYAMA, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Patent number: 7872308Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the sType: GrantFiled: December 10, 2008Date of Patent: January 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Publication number: 20100013010Abstract: An impurity concentration profile in a vertical direction of a p type base contact layer of a power semiconductor device has a two-stage configuration. In other word, the impurity concentration profile is highest at an upper face of the p type base contact layer, has a local minimum value at a position other than the upper face and a lower face of the base contact layer, and has a local maximum value at a position lower than the position of the local minimum value.Type: ApplicationFiled: July 14, 2009Publication date: January 21, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Miwako AKIYAMA, Yusuke KAWAGUCHI, Yoshihiro YAMAGUCHI
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Publication number: 20090242977Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.Type: ApplicationFiled: March 20, 2009Publication date: October 1, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yusuke KAWAGUCHI, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase
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Publication number: 20090184352Abstract: A semiconductor device includes: a semiconductor substrate; a lateral MOSFET formed in an upper portion of a first region of the semiconductor substrate; a vertical MOSFET formed in a second region of the semiconductor substrate; a backside electrode formed on a lower surface of the semiconductor substrate and connected to a lower region of source/drain regions of the vertical MOSFET; and a connecting member penetrating the semiconductor substrate and connecting one of source/drain regions of the lateral MOSFET to the backside electrode.Type: ApplicationFiled: January 16, 2009Publication date: July 23, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiro YAMAGUCHI, Yusuke KAWAGUCHI, Miwako AKIYAMA
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Publication number: 20090146209Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the sType: ApplicationFiled: December 10, 2008Publication date: June 11, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Publication number: 20090127616Abstract: A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant.Type: ApplicationFiled: November 6, 2008Publication date: May 21, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Miwako AKIYAMA, Yusuke KAWAGUCHI, Yoshihiro YAMAGUCHI
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Patent number: 7485921Abstract: This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.Type: GrantFiled: February 13, 2007Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kawaguchi, Yoshihiro Yamaguchi, Syotaro Ono, Miwako Akiyama
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Publication number: 20080299725Abstract: A method of manufacturing semiconductor devices comprises forming an semiconductor layer of the first conduction type on a substrate of the first conduction type; forming an anti-oxidizing layer on the surface of the semiconductor layer of the first conduction type, the anti-oxidizing layer having an aperture only through a region for use in formation of a guard ring layer of the second conduction type; forming the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type through implantation of ions into a surface where said anti-oxidizing layer is formed; forming an oxide layer at least in the aperture; forming a base layer of the second conduction type adjacent to the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type; and forming a diffused layer of the first conduction type through implantation of ions into the base layer of the second conduction type.Type: ApplicationFiled: May 28, 2008Publication date: December 4, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Miwako AKIYAMA, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Publication number: 20080283909Abstract: A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate electrode buried in the trench via the gate insulating film, and a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region.Type: ApplicationFiled: May 16, 2008Publication date: November 20, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Miwako Akiyama, Yusuke Kawaguchi, Yoshihiro Yamaguchi
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Patent number: RE46204Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.Type: GrantFiled: March 31, 2015Date of Patent: November 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kawaguchi, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase