Patents by Inventor Mizue Kitada
Mizue Kitada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7135718Abstract: A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the outermost one reaches these relay diffusion layers, and then the outer guard ring portions. The width of the distance between the guard ring portions is shorter where the relay diffusion layers are provided. For the width of the relay diffusion layers, the depletion layer reaches the outer guard ring portions with a lower voltage than the conventional structure.Type: GrantFiled: February 20, 2003Date of Patent: November 14, 2006Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Mizue Kitada, Kosuke Ohsima, Shinji Kunori, Toru Kurosaki
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Publication number: 20060063335Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.Type: ApplicationFiled: October 19, 2004Publication date: March 23, 2006Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Publication number: 20050224848Abstract: An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.Type: ApplicationFiled: April 4, 2005Publication date: October 13, 2005Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido
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Patent number: 6906355Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.Type: GrantFiled: October 3, 2003Date of Patent: June 14, 2005Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Patent number: 6876034Abstract: A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.Type: GrantFiled: June 27, 2003Date of Patent: April 5, 2005Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Patent number: 6841825Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.Type: GrantFiled: June 2, 2003Date of Patent: January 11, 2005Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Patent number: 6768138Abstract: The invention relates to technology improving the withstand voltage of a Schottky diode. With a diode of the present invention, the distance a between the long sides of the narrow groove withstand voltage portions and the inner ring circumference of the intermediate withstand voltage portion is set to twice the distance b between the short sides of the narrow groove withstand voltage portions and the inner ring circumference of the intermediate withstand voltage portion. Furthermore, the distance c between the inner ring circumference of the innermost outer withstand voltage portions and the outer ring circumference of the intermediate withstand voltage portion, the distance u between the adjacent outer withstand voltage portions, and the distance d between the adjacent narrow groove withstand voltage portions are all equal to the distance a.Type: GrantFiled: February 19, 2003Date of Patent: July 27, 2004Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Mizue Kitada, Kosuke Ohsima, Shinji Kunori
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Publication number: 20040070002Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.Type: ApplicationFiled: October 3, 2003Publication date: April 15, 2004Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Patent number: 6706615Abstract: A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.Type: GrantFiled: March 31, 2003Date of Patent: March 16, 2004Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Mizue Kitada, Toshiyuki Takemori, Shinji Kunori
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Publication number: 20040021195Abstract: A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.Type: ApplicationFiled: June 27, 2003Publication date: February 5, 2004Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Publication number: 20030227051Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.Type: ApplicationFiled: June 2, 2003Publication date: December 11, 2003Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
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Publication number: 20030203576Abstract: A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.Type: ApplicationFiled: March 31, 2003Publication date: October 30, 2003Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Mizue Kitada, Toshiyuki Takemori, Shinji Kunori
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Publication number: 20030160262Abstract: A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the outermost one reaches these relay diffusion layers, and then the outer guard ring portions. The width of the distance between the guard ring portions is shorter where the relay diffusion layers are provided. For the width of the relay diffusion layers, the depletion layer reaches the outer guard ring portions with a lower voltage than the conventional structure.Type: ApplicationFiled: February 20, 2003Publication date: August 28, 2003Inventors: Mizue Kitada, Kosuke Ohsima, Shinji Kunori, Toru Kurosaki
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Patent number: 6573559Abstract: A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.Type: GrantFiled: February 28, 2001Date of Patent: June 3, 2003Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Mizue Kitada, Toshiyuki Takemori, Shinji Kunori
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Publication number: 20030042555Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.Type: ApplicationFiled: July 18, 2002Publication date: March 6, 2003Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
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Patent number: 6404032Abstract: Trenches are formed in the surface of a second semiconductor layer of a first conductivity type. A semiconductor filled material of a second conductivity type is filled in the trench. A Schottky metal electrode is formed on the surface of the second semiconductor layer and the surface of the semiconductor filled material. A Schottky junction is formed between the Schottky metal electrode and the second semiconductor layer. An ohmic contact is formed between the Schottky metal electrode and the semiconductor filled material. An avalanche breakdown voltage is increased when the impurity concentration of the second semiconductor layer and the semiconductor filled material and the interval between the trenches are set such that both the second semiconductor layer interposed between the semiconductor filled materials and the semiconductor filled material are completely depleted when the Schottky junction is reverse biased.Type: GrantFiled: March 30, 2001Date of Patent: June 11, 2002Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Mizue Kitada, Shinji Kunori
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Publication number: 20010052617Abstract: A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.Type: ApplicationFiled: February 28, 2001Publication date: December 20, 2001Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTDInventors: Mizue Kitada, Toshiyuki Takemori, Shinji Kunori