Abstract: A hybrid electric vehicle includes an internal combustion engine configured to provide power to traction wheels, and a controller. The controller is configured to, in response to the engine being off and a power request exceeding an engine-start threshold, delay an engine start when vehicle speed is below a predetermined value. Delaying an engine start may include providing an engine-start-threshold offset. The offset decreases as vehicle speed increases. The engine is started when the power request exceeds a sum of the engine-start threshold and the engine-start-threshold offset.

Abstract: A hybrid electric vehicle includes an internal combustion engine configured to provide power to traction wheels, and a controller. The controller is configured to, in response to the engine being off and a power request exceeding an engine-start threshold, delay an engine start when vehicle speed is below a predetermined value. Delaying an engine start may include providing an engine-start-threshold offset. The offset decreases as vehicle speed increases. The engine is started when the power request exceeds a sum of the engine-start threshold and the engine-start-threshold offset.

Abstract: A system and method for controlling a powertrain in a vehicle includes controlling a speed of an engine in the vehicle using a first engine speed control when an accelerator pedal position is less than a first predetermined position and a battery discharge limit of a battery in the vehicle is at least a predetermined discharge limit. The speed of the engine is controlled using a second engine speed control different from the first engine speed control when the accelerator pedal position is less than the first predetermined position and the battery discharge limit is less than the predetermined discharge limit.

Abstract: A system and method for controlling a powertrain in a vehicle includes controlling a speed of an engine in the vehicle using a first engine speed control when an accelerator pedal position is less than a first predetermined position and a battery discharge limit of a battery in the vehicle is at least a predetermined discharge limit. The speed of the engine is controlled using a second engine speed control different from the first engine speed control when the accelerator pedal position is less than the first predetermined position and the battery discharge limit is less than the predetermined discharge limit.

Abstract: A parallel interleaver that operates to interleave convolutionally and turbo encoded data packets is described. Packets are divided into subpackets and interleaved in parallel for improved performance. The Pruned Bit Reversal Interleaver (PBRI) function used to generate interleaver addresses is invertible such that its inverse function can be used to generate de-interleaver addresses. For convolutionally encoded subpackets, encoder output bits are demultiplexed into three sequences V0, V1, V2 with the first bit going to V0, the second bit going to V1, the third going to V2, and the fourth to V0, etc. Next, each of the three sequences is bit-permuted independently using PBRIs to generate the sequences ?(V0), ?(V1), ?(V2). For turbo encoded subpackets, the encoder NT output data bits are demultiplexed into five sequences U, V0, V1, V?0, V?1. Next, the demultiplexed sequences are bit-permuted using five PBRIs into three separate interleaved blocks, denoted as ?(U), ?(V0/V?0), and ?(V1/V?1).

Abstract: Convolutional encoding throughput is increased by partitioning input information bits into a plurality of blocks that are convolutionally encoded in parallel. A plurality of convolutional encoding operations which have respective initial encode states that are mutually different from one another are applied in parallel to one of the blocks to produce a respectively corresponding plurality of convolutional encoding results. One of the convolutional encoding results is selected based on a convolutional encoding operation applied to another of the blocks.

Abstract: A parallel lookahead pruned bit-reversal interleaver algorithm and architecture have been proposed. The algorithm interleaves a packet of length N in at most log(N)?1 steps compared to N steps using existing sequential algorithms, and has a simple architecture amenable for high-speed applications. The proposed algorithm is valuable for emerging wireless standards especially those that employ PBRI channel (de-)interleavers on long packets in reducing interleaving latency on the transmitter side and deinterleaving latency on the receiver side.

Abstract: A parallel interleaver that operates to interleave convolutionally and turbo encoded data packets is described. Packets are divided into subpackets and interleaved in parallel for improved performance. The Pruned Bit Reversal Interleaver (PBRI) function used to generate interleaver addresses is invertible such that its inverse function can be used to generate de-interleaver addresses. For convolutionally encoded subpackets, encoder output bits are demultiplexed into three sequences V0, V1, V2 with the first bit going to V0, the second bit going to V1, the third going to V2, and the fourth to V0, etc. Next, each of the three sequences is bit-permuted independently using PBRIs to generate the sequences ?(V0), ?(V1), ?(V2). For turbo encoded subpackets, the encoder NT output data bits are demultiplexed into five sequences U, V0, V1, V?0, V?1. Next, the demultiplexed sequences are bit-permuted using five PBRIs into three separate interleaved blocks, denoted as ?(U), ?(V0/V?0), and ?(V1/V?1).

Abstract: A parallel lookahead pruned bit-reversal interleaver algorithm and architecture have been proposed. The algorithm interleaves a packet of length N in at most log(N)?1 steps compared to N steps using existing sequential algorithms, and has a simple architecture amenable for high-speed applications. The proposed algorithm is valuable for emerging wireless standards especially those that employ PBRI channel (de-)interleavers on long packets in reducing interleaving latency on the transmitter side and deinterleaving latency on the receiver side.

Abstract: Apparatus and methods for calculating constant amplitude zero auto-correlation sequences are disclosed. One method includes calculating an argument of trigonometric functions used for calculating a constant amplitude zero auto-correlation sequence based at least on additive recursion of an input sequence root constant and without multiplication by a variable. A constant amplitude zero auto-correlation sequence is then computed using a CORDIC algorithm configured to calculate trigonometric functions used in determining the sequence without performing multiplication operations and based on the calculated argument. The disclosed methods and apparatus may be applied, in particular, to efficiently computing Zadoff-Chu sequences in preamble detection in particular physical random access channels in Long Term Evolution LTE communication systems. By allowing computation of such sequences, memory requirements can be reduced.

Abstract: Convolutional encoding throughput is increased by partitioning input information bits into a plurality of blocks that are convolutionally encoded in parallel. A plurality of convolutional encoding operations which have respective initial encode states that are mutually different from one another are applied in parallel to one of the blocks to produce a respectively corresponding plurality of convolutional encoding results. One of the convolutional encoding results is selected based on a convolutional encoding operation applied to another of the blocks.