Abstract: A PLL-based frequency synthesizer is provided. In accordance with one aspect, a phase locked loop is provided that comprises a phase detector, a loop filter, a voltage controlled oscillator, and a feedback circuit. The phase detector has as inputs a reference frequency signal and a feedback signal. The phase detector is operable to generate a phase detection signal based on a comparison of phases between the reference frequency signal and the feedback signal. The loop filter is coupled to the phase detector for receiving the phase detection signal and generates an output voltage in response to the phase detection signal. The voltage controlled oscillator is coupled to the output voltage of the loop filter and generates a local oscillator signal. The feedback circuit is coupled to the local oscillator signal and generates the feedback signal. The feedback circuit comprises a sampling circuit.

Abstract: A PLL-based frequency synthesizer is provided that includes a phase detector, a loop filter, a VCO, a sampler and filter system, and a frequency divider. This architecture reduces the high division ratio (N) necessary in a classical PLL-based frequency synthesizer while maintaining low phase-noise. This is achieved through sub-sampling the VCO output signal in the feedback path. The sampler is placed in the feedback loop following the VCO and is clocked at a low frequency (sub-sampling). The output of the sampler is the beat frequency between the VCO frequency and the sampling clock (in addition to harmonics that are filtered-out by a low-pass filter (LPF)). The LPF in the feedback loop attenuates any tones resulting from the sampling operation. A frequency divider is then used to bring down the feedback signal to the frequency of the phase detector input.

Abstract: A direct digital frequency synthesizer for generating a digital sine or cosine function waveform receive digital input. Memory stores digital samples along portions of sine and cosine function waveforms. The memory outputs the digital samples in response to a first portion of the digital input. Control logic is responsive to the digital input and controls the output of the digital samples from the memory to allow digital samples along a complete cycle of the sine or cosine function waveform to be output even though only portions of the sine and cosine function waveforms are stored in the memory. A linear interpolator receives a second portion of the digital input and modifies digital samples output by the memory to generate intermediate digital samples between the digital samples stored in the memory to improve accuracy.

Abstract: Several low power, low voltage swing, BiCMOS circuits for used in high speed chip-to-chip communications are described. In particular a BiCMOS low voltage swing transceiver comprising a driver and a receiver with low on-chip power consumption is reported. Operating at 3.3.V, the universal transceiver can drive and receive low voltage swing signals with termination voltages ranging from 5V down to 2V, without using external reference voltages and at frequencies exceeding 1 GHz. On-chip power consumption is much lower than that of known CML/ECL type transceivers having comparable speeds.

Abstract: A low power high performance adder using a conditional sum adder (CSA) architecture and complementary pass logic (CPL) implementation. The adder comprises a plurality of blocks, each block including a conditional sum cell and an output multiplexer. Each block except the first, also comprises a block of 2:1 multiplexers intermediate the conditional sum cell and the output multiplexer. The adder according to the present invention operates with lower power consumption and at greater speed than prior art adder architectures.

Abstract: A SRAM includes an ECL input buffer connected between an address bus and a W-OR predecoder array. The logic output of the W-OR predecoder array is applied to a level translator array and level shifted. The level shifted output of the level translator array is supplied to a plurality of self-resetting word-line decoder and driver (WLDD) circuits. The WLDD circuits supply activation pulses to selected blocks of memory in a memory cell array. Sense amplifiers sense and latch-in the data stored in the activated selected blocks of memory. The design of the W-OR predecoder array, level translator array, WLDD circuits and sense amplifiers is such to reduce the overall power consumption of the SRAM.

Abstract: Disclosed is a field effect current mode logic gate comprised of a current source for supplying a constant current, and a differential amplifier having first and second branches for passing respective portions of the constant current. The first branch includes a plurality of parallel-coupled or serially-coupled enhancement field effect transistors having a positive threshold voltage and having respective gates for receiving respective input logic signals; and the second branch includes a depletion field effect transistor having a negative threshold voltage, and a grounded gate. The magnitudes of the current portions in the first and second branches are representative of the magnitude of the input logic signals relative to the positive threshold voltage plus the absolute value of the negative threshold voltage.

Abstract: Disclosed is an improved static memory cell comprised of first and second conductive means for carrying respective bias voltages in the cell, a third conductive means for carrying an input/output voltage signal in the cell, and a Lambda diode coupled between the first and third conductive means for there providing a negative dynamic resistance whenever the input/output voltage signal is within a predetermined range between the bias voltages on the first and second conductive means, with the improvement being a voltage dependent resistance means coupled between the second and third conductive means for there providing a negative dynamic resistance in response to at least some of the input/output voltages within said range.