Patents by Inventor Mohammad Farnaam

Mohammad Farnaam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4962060
    Abstract: An interconnect (16',18', 18"), whose interlevel contacts comprise refractory (10) to refractory or refractory to semiconductor substrate (13) interfaces, comprises patterned refractory core portions (10), consisting of tungsten or molybdenum, having top portions (10a) and opposed side portions (10b), provided with sidewall spacers (32a) of aluminum, gold or copper or alloys thereof and formed on surfaces (12a) of insulating layers (12). The sidewall spacers afford lateral low resistivity cladding of the refractory portions as well as suppression of the electromigration failure modes of voiding and whiskering, while leaving the top portion of the core portions available for refractory to refractory contacts and the bottom portion of the core portions available for refractory to refractory or refractory to silicon contacts.
    Type: Grant
    Filed: May 2, 1989
    Date of Patent: October 9, 1990
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jack Sliwa, Mohammad Farnaam, Pankaj Dixit, Lewis N. Shen
  • Patent number: 4960732
    Abstract: A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry.The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon.
    Type: Grant
    Filed: November 14, 1989
    Date of Patent: October 2, 1990
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pankaj Dixit, Jack Sliwa, Richard K. Klein, Craig S. Sander, Mohammad Farnaam
  • Patent number: 4884123
    Abstract: A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry. The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon.
    Type: Grant
    Filed: February 19, 1987
    Date of Patent: November 28, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pankaj Dixit, Jack Sliwa, Richard K. Klein, Craig S. Sander, Mohammad Farnaam
  • Patent number: 4847674
    Abstract: An interconnect (16', 18', 18"), whose interlevel contacts comprise refractory (10) to refractory or refractory to semiconductor substrate (13) interfaces, comprises patterned refractory core portions (10), consisting of tungsten or molybdenum, having top portions (10a) and opposed side portions (10b), provided with sidewall spacers (32a) of aluminum, gold or copper or alloys thereof and formed on surface (12a) of insulating layers (12). The sidewall spacers afford lateral low resistivity cladding of the refractory portions as well as suppression of the electromigration failure modes of voiding and whiskering, while leaving the top portion of the core portions available for refractory to refractory contacts and the bottom portion of the core portions available for refractory to refractory or refractory to silicon contacts.
    Type: Grant
    Filed: March 10, 1987
    Date of Patent: July 11, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jack Sliwa, Mohammad Farnaam, Pankaj Dixit, Lewis N. Shen
  • Patent number: 4820611
    Abstract: Reflection of incident optical radiation (18) from a highly reflective metal layer (12), such as aluminum or titanium, into a photoresist layer (14) is reduced by interposing a layer of titanium nitride (16) between the metal and photoresist layers. The thickness of the TiN layer depends on the wavelength of the optical radiation used to expose the photoresist and on the optical properties of the underlying metal layer. Reflectance of less than about 2% may be achieved using the TiN layer in conjunction with aluminum and less than about 5% in conjunction with titanium, in accordance with the invention. If left in place after patterning an underlying aluminum layer, the TiN layer also serves to suppress hillock formation in the aluminum layer.
    Type: Grant
    Filed: April 24, 1987
    Date of Patent: April 11, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William H. Arnold, III, Mohammad Farnaam, Jack Sliwa