Patents by Inventor Mohammad S. Nasser

Mohammad S. Nasser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Complimentary bipolar/CMOS fabrication method
    Patent number: 5262345
    Abstract: A complementary bipolar process enables both PNP and NPN transistors to be added to a CMOS process with a minimum of extra fabrication steps. The P-well of a CMOS process is used for the collector region of the PNP transistor and the "down isolation" for the NPN transistor. A buried P diffusion provides "up" isolation for the NPN transistor and buried collector for the PNP transistor. A method for increasing the NPN buried collector to "up" isolation breakdown voltage is described which uses multiple N type impurities.
    Type: Grant
    Filed: May 15, 1992
    Date of Patent: November 16, 1993
    Assignee: Analog Devices, Inc.
    Inventors: Mohammad S. Nasser, Saurabh M. Desai, Derek F. Bowers