Abstract: A method for reducing a disparity between even and odd eye characteristics in recovered data includes: receiving an input serial data stream; performing independent data slicing of even and odd components in the serial data stream to generate corresponding even and odd discrete-time data samples, respectively; performing independent error slicing of even and odd components in the serial data stream to generate corresponding even and odd discrete-time error samples, respectively; deserializing the even and odd discrete-time data and error samples to generate the recovered data and recovered error, respectively; and controlling respective offsets for error slicing of the even and odd components independently so as to reduce the disparity between even and odd eye characteristics in the recovered data.

Abstract: A method for facilitating acquisition of a received reference clock signal in a CDR system includes steps of: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero.

Abstract: In training a SERDES, a Common Electrical Interface (CEI) training frame, having certain bits of information embedded therein, is transmitted over a path which comprises transmitter, channel, and receiver components. The present invention analyzes the resulting received signal and determines the effective aggregate channel impulse response of these three components. The invention then determines an estimate of the inverse of this aggregate channel and uses this determination to reduce distortions that have been introduced into a signal that has been transmitted over the path.

Abstract: A pre-distorter that compensates for amplitude and phase distortion created by an amplifier. During a training session, the amplifier is stimulated with input signals of pre-selected amplitude and phase at various temperatures and the amplifier output is captured and converted into data sets. Polynomials are then fitted to the data sets and inverses of the polynomials are determined. The coefficients of the inverse polynomials are then saved for each temperature. During operation, the amplifier temperature is predicted based on the amplifier input signal and the coefficients associated with the predicted temperature are selected to be applied to the input signal to compensate for amplitude and phase distortion caused by the amplifier.

Abstract: A pre-distorter that compensates for amplitude and phase distortion created by an amplifier. During a training session, the amplifier is stimulated with input signals of pre-selected amplitude and phase at various temperatures and the amplifier output is captured and converted into data sets. Polynomials are then fitted to the data sets and inverses of the polynomials are determined. The coefficients of the inverse polynomials are then saved for each temperature. During operation, the amplifier temperature is predicted based on the amplifier input signal and the coefficients associated with the predicted temperature are selected to be applied to the input signal to compensate for amplitude and phase distortion caused by the amplifier.

Abstract: An efficient polyphase half rate finite impulse response (FIR) filter module includes an odd/even sample delay line. The odd/even sample delay line includes two parallel paths of delays corresponding respectively to odd and even sample processing, i.e., every other sample. A first input sample is presented to the first register phase in the odd/even sample delay line and is fed directly to the third register phase bypassing the second register phase, the third register phase feeds directly into the fifth register phase, and so on until the ninth register phase of the odd/even sample delay line feeds directly into the eleventh register phase bypassing the tenth register phase. A second input sample skips over the first register phase and is presented directly to the second register phase in the odd/even sample delay line.

Abstract: In accordance with one embodiment of the invention, a method for compensating frequency offset errors in a communication system comprising the steps of receiving a plurality of signal bursts that correspond to a plurality of transmitted signal bursts. A channel estimation is performed based on at least the predetermined information contained in the transmitted signal bursts. For each received signal sample, a Viterbi decoding is performed using the channel estimations. A final updated Viterbi state cost is calculated for each received signal. A good equalizer quality signal is provided when the final updated Viterbi state cost is below a given threshold. The transmitted signal bursts are then reconstructed from the receive signal bursts, by applying the channel estimation to reencode the decoded signal bursts retrieved from the Viterbi decoder. The quality of the channel estimation is determined based on a given threshold of bit error rate in a plurality of received signal bursts.

Abstract: A QAM data signal timing recovery loop feedback element provides a fixed sampling time offset adjustment to two continuously variable digital rate interpolators/decimators to produce a quadrature output stream at a programmed rational rate multiple of the actual baud rate of the received data signal. The continuously variable digital rate interpolators/decimators are configured at startup so as to produce output streams at the same programmed rational rate multiple of the nominal baud rate of the anticipated received data signal, assuming the fs sample timing offset adjustment stream provided by the timing recovery feedback element to be identically 0. The “nominal” fixed sampling rate fs of the received analog input signal need not be rationally related to the nominal baud rate of the anticipated received data signal.

Abstract: The invention includes a method of identifying an extremum value and an index in a group of values where each value has an associated index. A count register is initialized to an initial count. A value from the group as well as a predetermined value are provided simultaneously to an arithmetic logic unit and a multiplexer. The value from the group and the predetermined value are compared in the arithmetic logic unit. A selector is set to one of a first or second logic state. In the first logic state the selector selects a minimum; in the second logic state the selector selects a maximum. One of the value and the predetermined value are selected as an extremum based on a flag set by the comparison in the arithmetic logic unit and the selector. The predetermined value is replaced with the extremum and the count register count is stored when the selector is set to a first state and the value is less than the predetermined value.

Abstract: In a receiver, a digital automatic gain control circuit receives a series of digital samples representing at least one of an in-phase component and a quadrature component of a received signal, and provides scaled in-phase components and scaled quadrature components to an equalizer. The digital automatic gain control circuit includes a gain updating unit that receives a value representing at least one of an in-phase component and a quadrature component, receives a target reference value, and updates a gain value based on a difference therebetween. The digital automatic gain control circuit also includes a scalar that scales the received signal based on the updated gain value.

Abstract: A digital automatic gain control circuit for a receiver includes an averaging block and an adjustment block. The averaging block receives a length of a digital sample stream that represents an incoming analog signal and produces an absolute average signal. The adjustment block receives the absolute average signal and a reference signal and outputs an adjustment signal for controlling gain. The adjustment signal is based on a difference between the absolute average signal and the reference signal. In an alternative embodiment, a method of controlling gain according to the invention includes the steps of calculating an absolute average of an incoming signal, and comparing the absolute average to a reference to produce an adjustment signal based on a difference between the absolute average and the reference.

Abstract: There is disclosed, a method and apparatus for processing a signal in a pipeline. The method includes retrieving a present state cost. Simultaneously with receiving the present state cost, an estimated symbol and a received symbol are obtained, a difference between the received and estimated symbols is found, the difference between the received and esitmated symbols is squared, and the present state cost is added to the squared difference to generate a next state cost. The apparatus includes hardware to carry out the method.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of compensating for Doppler error in a wireless communications system employing Viterbi decoding comprises the steps of: for each signal sample in a first predetermined-sized grouping of received signal samples, performing a parallel Viterbi update and short symbol decode; and for a second predetermined-sized grouping, forming by pipeline processing an estimate of the Doppler error in accordance with the parallel short traceback decoding performed for the first grouping, and adjusting each signal sample in the second grouping in accordance with the estimated Doppler error.Briefly, in accordance with another embodiment of the invention, a Viterbi traceback reconstructed signal sample index comprises: a state counter, a traceback shift register (TBSR); a signal reconstruction table; and a comparator coupled in a configuration so as to provide the sign bit to the TBSR from a comparison of binary digital signals.

Abstract: Briefly, in accordance with one embodiment of the invention, an oscillator frequency offset error estimator at the receiving end of a wireline communications system comprises: a phase comparator adapted to compare two successive signal samples, each signal sample being derived from a baseband signal transmitted via the wireline communications system. The phase comparator is further adapted to have at least one of the two signal samples provided along a signal path through a phase shifter and a time delay.

Abstract: Briefly, in accordance with one embodiment of the invention, a coarse frequency burst detector for use at the receiving end of a wireline communications system comprises: a digital signal filter adapted to filter a component of decoded signal samples, the decoded signal samples being derived from a baseband signal transmitted via the wireline communications system; and a threshold detector adapted to threshold the signal level of the filtered component of the decoded signal samples with respect to a substantially predetermined level. In accordance with another embodiment, a method of detecting at the receiving end of a wireline communications system a frequency burst in a baseband signal transmitted via the wireline communications system comprises the steps of: filtering a component of a decoded signal derived from the baseband signal transmitted via the wireline communications system; and thresholding the filtered component.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of compensating for Doppler error in a wireless communications system employing Viterbi decoding comprises the steps of: for each signal sample in a first predetermined-sized grouping of received signal samples, performing a parallel Viterbi update and short symbol decode; and for a second predetermined-sized grouping, forming by pipeline processing an estimate of the Doppler error in accordance with the parallel short traceback decoding performed for the first grouping, and adjusting each signal sample in the second grouping in accordance with the estimated Doppler error.Briefly, in accordance with another embodiment of the invention, a Viterbi traceback reconstructed signal sample index comprises: a state counter, a traceback shift register (TBSR); a signal reconstruction table; and a comparator coupled in a configuration so as to provide the sign bit to the TBSR from a comparison of binary digital signals.

Abstract: There is an equalizer or a receiver including an equalizer which has means to factor detected symbols transmitted over a transmission channel into a magnitude portion and a repetitive phase portion. The receiver further has means to generate modified tap weights by multiplying the repetitive phase portion by tap weights representative of the channel. Modified tap weights are generated by multiplying the repetitive phase portion by tap weights representative of the channel. The modified tap weights are convolved with bits of possible states to generate possible transmitted symbols. A maximum likelihood sequence estimation is performed on the possible transmitted symbols comparing each possible transmitted symbol to a received symbol to generate an MLSE detected symbol. The detected symbol is multiplied by a rotating vector to generate a decoded symbol.