Abstract: A flip chip optoelectronic device assembly includes a hollow, cylindrical spacer between an optical source in the substrate and the active surface of the chip, which precludes attenuation of the signal and allows direct transmission through air. An underfill material fills the space between chip and substrate, thereby allowing substrates which are not necessarily matched in thermal expansion to the chips, and the spacer acts as a dam to prevent ingress of underfill material into the optical path. The spacer not only allows use of conventional underfill materials to support the interconnection joints and thermal mismatch, but also defines a fixed “z” axis distance between substrate and chip.

Abstract: Electronic devices of improved reliability having a substrate of electrically insulating material, further an integrated circuit chip with a periphery and a surface. Using a layer of polymeric material, the chip surface is mounted on the substrate surface. The polymeric material protrudes beyond the chip periphery and spreads some distance along the substrate surface. A metal layer is on the substrate surface, this layer is shaped as a band around the chip periphery; the band has an inner edge near the chip periphery, and an outer edge near the contour of the polymer protrusion. This metal band serves as a guard ring to stop any nascent crack propagating in the polymer protrusion.

Abstract: A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

Abstract: A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

Abstract: A method for assembling FCBGA packages having fewer heating cycles and process steps than prior art is made possible through the use of a novel carrier pallet. The pallet includes recesses which mirror external solder ball contacts of the BGA package under assembly. A solder ball is positioned in each recess, a chip carrier substrate aligned and positioned atop the solder, a chip having flip chip contacts aligned to the opposite surface of the chip carrier, and the assemblage subjected to heating and cooling as required to connect both sets of contacts in a single thermal cycle. As required by the device under assembly, an underfill material and a protective cover may be included in the assembly process while making use of the carrier pallet, and without moving the devices. The carrier pallet may be used for transporting and attaching solder contacts of many types of BGA or CSP devices. Yield, reliability, and cost advantages are made possible by the invention.

Abstract: A method for testing a cell in a device for reliability is disclosed. The cell us coupled to a reference voltage and a current source. The method and system comprises measuring a mirrored current through the device at first predetermined gate voltage and measuring a mirrored current through the device at a second predetermined voltage. The method and system includes determining the threshold voltage of the cell and heating the device for a predetermined period of time. Finally, the method and system includes calculating a new threshold voltage if the measured mirrored current is different from the previously measured current. Accordingly, a system and method in accordance with the present invention addresses this drift problem by testing the characteristics of the memory array on a bit by bit basis. A system and method in accordance with the present invention includes a mirrored current source arrangement.

Abstract: A signal processing circuit is disclosed. The signal processing circuit comprises a sensor for receiving a voltage and providing a first signal based on at least one parameter. The signal processing circuit further includes a first digital to analog converter (DAC) for providing a supply voltage to the summer and a second DAC for providing a voltage (V.sub.tc) which is dependent upon the supply voltage and a variation in temperature of the supply voltage. The signal processing circuit also includes a summer coupled to the first and second DACs for receiving the first signal and providing a first output and a gain circuit for receiving the first output and providing an output voltage. In accordance with the system and method of the present invention, a voltage V.sub.tc which is dependent on the supply voltage and a variation in temperature of the supply voltage can be utilized advantageously to minimize the number of DACs in the signal processing system.

Abstract: A method and system for providing a filter having an increased speed and decreased settling time are disclosed. The method and system comprise summing means for adding and subtracting. The method and system further comprise means coupled to the summer for providing a delay; and a clock coupled to the delay providing means. The clock determines a number of samples during a predetermined time. The clock is operated at a plurality of frequencies such that the total number of samples during the predetermined time is a predetermined number. According to the method and system disclosed, the filter has an increased speed. The increased speed of the filter can operate to extend the lifetime of power devices.

Abstract: A digital compensation circuit for calibrating a sensor is described. The compensator circuit includes a serial communication circuit for receiving data relating to a plurality of parameters and a compensation circuit coupled to serial communication circuit for providing piece-wise linear compensation of a temperature coefficient (TC). In one embodiment, the compensation circuit further includes a detector for detecting a threshold for a digital temperature and providing an output and a plurality of registers coupled to the detector and the serial communication circuit, a first plurality of registers for providing a first value if the digital temperature is above the threshold, a second of the plurality of registers for providing a second value if the digital temperature is below the threshold.

Abstract: A method and system for calibrating a sensor is disclosed The method and system include receiving data relating to a plurality of temperature parameters and providing polynomial compensation of a temperature coefficient (TC). When providing polynomial compensation of the temperature coefficient, the method and system further include providing a first output and adding a second value to the first output. The first output is a distal temperature multiplied by a first value.

Abstract: A circuit and method for avoiding latch up in an integrated circuit in which the base-emitter junction of a parasitic bipolar transistor forming part of a parasitic SCR structure is monitored. If the forward bias of the monitored base-emitter junction approaches a predetermined value, the operation of the circuit is altered to prevent activation of the SCR.

Abstract: A sigma-delta analog-to-digital converter employs multiplexed single-loop modulators in parallel and respectively phased time-divided clocks. The parallel modulators have the effect of producing digital output at a high sampling frequency that is a multiple of the phased switching frequencies applied to the modulator circuits. In one preferred embodiment, four second-order sigma-delta modulators are driven in clocked phased sequence and combined by a multiplexor circuit. Another embodiment employs second-order modulators using RC integrators. A further embodiment replaces the multiplexor with an adder when in-phase modulator clocks are used, and the adder also acts as a simple low pass filter.

Abstract: The duration of time during which an AC power voltage sinusoidal waveform remains between negative voltage threshold -V1 volts, nominally 5% of negative peak voltage -V2 volts, and positive voltage threshold +V1 volts, nominally 5% of peak positive voltage +V2 volts, is detected. By the change in voltage with time exhibited by a sinusoidal waveform in the region of zero voltage crossing, the expected time duration between voltage thresholds in approximately 5% of one-half period of such sinusoidal waveform. If the actual time between voltage thresholds exceeds (nominally) twice this value, or 10% of one-half period, then a power black-out condition is sensed, and a power fault signal is produced.

Abstract: Disclosed is an improved efficiency switching voltage converter system wherein the semiconductor switching device employed therein is provided with increased gate drive by selectively applying the most effective driving voltage available in the system.

Abstract: Disclosed is an improved efficiency switching voltage converter system wherein the semiconductor switching device employed therein is provided with increased gate drive by selectively applying the most effective driving voltage available in the system.