Abstract: A cache coherent interconnect connected to one or more agents, using Network Interface Units (NIUs), and also having one or more internal modules, such as a directory, is provided with one or more message builders and message receivers. These message builders and message receivers are provided as additional hardware IP blocks incorporated into the various NIUs and modules. When an agent signals an intention to enter/exit the cache coherent interconnect, a message communicating this information is generated using message builders, and transmitted using the interconnect wiring as a “virtual wire” to one or more message receivers associated with directories that need to be aware of the entry/exit transition of the agent. The directories are provided with tracking engines to manage the entry/exit information and status of the agent. Interconnects may include a broadcast engine to provide distribution to, and aggregate acknowledgements from, a single source to multiple destinations.

Abstract: A cache coherent interconnect connected to one or more agents, such as CPUs, GPUs, Peripherals, etc. using network interface units (NIUs), and having one or more internal modules, such as a directory, is provided with one or more event-to-message converters, and one or more message-to-event converters. When a particular event occurs within one of the agents or modules, a message is initiated and transmitted using the existing interconnect wiring to one or more agents or modules, which have associated NIUs, that need to be aware of the event. Response messages showing the status of the event-message may also be generated. Therefore, messages are sent when events occur, instead of constantly using bandwidth for status updates when no status is changing, making the interconnect more efficient and freeing up bandwidth. These converters are provided as additional hardware blocks incorporated into the various NIUs and modules.

Abstract: A system and method are disclosed for a cache IP that includes registers that are programmed through a service port. Service registers are selected from the registers to define an address range so that all cache lines within the address range can be flushed automatically using a control signal sent to a control register.

Abstract: A quality of service (QoS) management system and guarantee is presented. The QoS management system can be used for end to end data. More specifically, and without limitation, the invention relates to the management of traffic and priorities in a queue and relates to grouping transactions in a queue providing solutions to queue starvation and transmission latency.

Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

Abstract: A quality of service (QoS) management system and guarantee is presented. The QoS management system can be used for end to end data. More specifically, and without limitation, the invention relates to the management of traffic and priorities in a queue and relates to grouping transactions in a queue providing solutions to queue starvation and transmission latency.